UPGRADE YOUR BROWSER

We have detected your current browser version is not the latest one. Xilinx.com uses the latest web technologies to bring you the best online experience possible. Please upgrade to a Xilinx.com supported browser:Chrome, Firefox, Internet Explorer 11, Safari. Thank you!
Page Bookmarked
  1. Xilinx - All Programmable
  2. Support
  3. AR# 38571: Virtex-6 GTH Transceiver - Manually setting the tap values for the DFE

AR# 38571

Virtex-6 GTH Transceiver - Manually setting the tap values for the DFE

Description

This Answer Record contains the bit mappings for the DFE taps in the Virtex-6 GTH Transceiver.  

Solution

The DFE in the Virtex-6 GTH Transceiver has three taps.

The table below contains the bit mappings for these taps; the bits that enable overriding the auto-calibration, and the equalization gain settings.



DFE Impact

Attribute Location:

Tap 1 Value [4:0]:

RX_AEQ_VAL1_LANE[4:0]

Tap 1 Override:

RX_AEQ_VAL1_LANE [5]

Tap 2 Value [4:0]:

RX_AEQ_VAL1_LANE [10:6]

Tap 2 Override:

RX_AEQ_VAL1_LANE [11]

Tap 3 Value [4]:

RX_AEQ_VAL0_LANE [0]

Tap 3 Value [3:0]:

RX_AEQ_VAL1_LANE [15:12]

Tap 3 Override:
RX_AEQ_VAL0_LANE[1]

DFE Gain:
RX_AEQ_VAL0_LANE[5:4]

AGC Gain:
RX_AEQ_VAL0_LANE[3:2]


NOTE: Xilinx is only providing these bit locations for users who are interested in setting the feedback taps themselves.

Performance while manually modifying these bits depends on the use model.

For supported DFE use cases, see the Virtex-6 GTH Transceiver User's Guide (UG371).

Linked Answer Records

Associated Answer Records

Answer Number Answer Title Version Found Version Resolved
37414 Virtex-6 GTH Transceiver - Attribute updates for ES silicon N/A N/A
38596 Virtex-6 FPGA GTH Transceiver - Known Issues and Answer Records List N/A N/A
AR# 38571
Date 06/23/2017
Status Active
Type General Article
Devices
  • Virtex-6 CXT
  • Virtex-6 HXT