The DFE in the Virtex-6 GTH Transceiver has three taps.
The table below contains the bit mappings for these taps; the bits that enable overriding the auto-calibration, and the equalization gain settings.
DFE Impact | Attribute Location: |
Tap 1 Value [4:0]: | RX_AEQ_VAL1_LANE |
Tap 1 Override: | RX_AEQ_VAL1_LANE |
Tap 2 Value [4:0]: | RX_AEQ_VAL1_LANE |
Tap 2 Override: | RX_AEQ_VAL1_LANE |
Tap 3 Value [4]: | RX_AEQ_VAL0_LANE |
Tap 3 Value [3:0]: | RX_AEQ_VAL1_LANE |
Tap 3 Override: | RX_AEQ_VAL0_LANE |
DFE Gain: | RX_AEQ_VAL0_LANE |
AGC Gain: | RX_AEQ_VAL0_LANE |
NOTE: Xilinx is only providing these bit locations for users who are interested in setting the feedback taps themselves.
Performance while manually modifying these bits depends on the use model.
For supported DFE use cases, see the Virtex-6 GTH Transceiver User's Guide (UG371).
Answer Number | Answer Title | Version Found | Version Resolved |
---|---|---|---|
38596 | Virtex-6 FPGA GTH Transceiver - Known Issues and Answer Records List | N/A | N/A |
AR# 38571 | |
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Date | 06/23/2017 |
Status | Active |
Type | General Article |
Devices |