AR# 38608


12.2 System Generator: Black Box outputs must be delayed for simulation to run with combinational feedback error


When incorporating VHDL black boxes into a System Generator design and running simulation, users may encounter the following error:

Sysgen cannot simulate designs with combinational feedback

Reported by:

By default when generating a black box for Sysgen, the "xxxx_config.m" file is tagged as combinatorial logic with the following tag included in the config M-file.

% System Generator has to assume that your entity has a combinational feed through;
% if itdoesn't, then comment out the following line:

This means System Generator will treat the black box as combinatorial logic during simulation.


Options available to work around this issue:

1. Ensure all black box outputs have a delay block added to their path in the Sysgen MDL.
2. Prior to creating the black box, make sure all paths through the VHDL module contain at least one register to avoid combinatorial logic. If the user is sure all paths contain a synchronous element, then they can safely comment out the tag from the config M-file. (i.e. comment out this_block.tagAsCombinational;)

AR# 38608
Date 12/15/2012
Status Active
Type General Article
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