UPGRADE YOUR BROWSER

We have detected your current browser version is not the latest one. Xilinx.com uses the latest web technologies to bring you the best online experience possible. Please upgrade to a Xilinx.com supported browser:Chrome, Firefox, Internet Explorer 11, Safari. Thank you!
  1. Xilinx - Adaptable. Intelligent.
  2. Support
  3. AR# 38620: ISE 12.2 Pack Virtex-6 - Pack:2784 - Directed packing was unable to obey the user design constraint

AR# 38620

ISE 12.2 Pack Virtex-6 - Pack:2784 - Directed packing was unable to obey the user design constraint

Description

The following error is being received during Map:

ERROR:Pack:2784 - Directed packing was unable to obey the user design constraint
   (LUTNM=Transceiver/INST_PROCESSING_CHAIN.TRX_Data_Chain/INST_FFT_IFFT.FFT_IFF
   T_1/V6_FFT_Core_Gen.FFT_Core/blk00000003/U0/non_floating_point.arch_d.xfft_in
   st/pe_gen[3].natural_order_input.PE/delay_addr_bf2/SRL16_2) which requires
   combining the symbols listed below into a single SLICEM component.
...
The directed pack was not possible because:
   The top reasons for failure were:
           -> A legal placement was never found for shift register symbol
...
How can I resolve this error?

Solution

This is a known issue which has been resolved in ISE 12.3.

The issue can be worked around by disabling power optimization (Removing the -power switch) of Map.


AR# 38620
Date 07/30/2014
Status Active
Type General Article
Devices
  • Virtex-6 CXT
  • Virtex-6 HXT
  • Virtex-6 LX
  • More
  • Virtex-6 LXT
  • Virtex-6 SXT
  • Less
Tools
  • ISE Design Suite - 12.1
  • ISE Design Suite - 12.2
Page Bookmarked