AR# 38623: MIG Spartan-6 MCB - Why is ODT issued late by the MCB when operating in DDR2 mode 400 Mbps?
MIG Spartan-6 MCB - Why is ODT issued late by the MCB when operating in DDR2 mode 400 Mbps?
ODT (On-Die Termination) is a feature of the DDR2 SDRAM that allows the DRAM to turn on/off termination resistance via the ODT control pin. The ODT feature is designed to improve signal integrity of the memory channel by allowing the DRAM controller to independently turn on/off termination resistance for any or all DRAM devices.According to the JEDEC DDR2 spec, the input termination will be enabled about 2nCK after the ODT pin is registered high in the DRAM.
For DDR2 memory interfaces operating at 400 Mbps or below with a CAS latency of three,there might be overshoot on DQS on the first rising edge due to the ODT feature being enabled too late.
Because ofthe way that the MCB functions, the ODT pin will always go high at the same time that the WRITE command is issued to the DRAM.Since the ODT pin will always be triggered high at the same time that the WRITE command is sent to the DRAM, we will always enable the DRAM termination 2nCK after the WRITE command is sent.For most cases this is not an issue. However, a problem will occur when the CAS latency is set to three, as is the case when operating the memory interface at 400 Mbps or below. The write latency is equal to the CAS latency minus one (two when CAS latencyis three). Write latency is the time between when the WRITE command is registered and when the first rising edge of DQS is expected. Therefore, you might see overshoot when the first rising edge of DQS is being sent while the termination is being enabled.
You can work around this issue by changing the DDR2 interface frequency to greater than 400 Mbps which will change the CAS latency fromthree to four, thus enabling the memory input termination one clock cycle before the first rising edge of DQS.
Alternatively, you can work around the issue by manually modifying the Cx_MEM_CAS_LATENCY parameter in the MIG generated design fromthree tofour, which will also result in the input termination enabled one clock cycle before the rising edge of DQS. This requires that the DDR2 DRAM can support a CAS latency offour with a slower memory clock frequency and will reduce the throughput of the DDR2 memory.