AR# 38625

Design Assistant for PCI Express - How to determine all of the options used to generate a PCI Express core.

Description

This Answer Record shows how to determine the options in CORE Generator used to generate a PCI Express core when you only have the core generated files.

NOTE:This Answer Record is part of the Xilinx Solution Center for PCI Express(Xilinx Answer 34536). The Xilinx Solution Center for PCI Express is available to address all questions related to PCIe. Whether you are starting a new design with PCIe or troubleshooting a problem, use the Solution Center for PCIe to guide you to the right information.

Solution

PCI Express cores either generate an NGC or HDL source files. Despite the output file type, the options used to generate the files can be derived with only the generated files and the XCO is not necessary.

To regenerate a core it is still recommended to use the XCO; however, when the XCO is not available, then you can use the method described below.

If the core generated is an NGC, then you can run the ngc2edif command to generate an EDIF file. Then, search the EDIF for "CORE_GENERATION_INFO". This attribute will give you the options used to generate the core.

If the core generated is HDL source code, then the CORE_GENERATION_INFO attribute will be listed in the top level HDL file.

Revision History

07/30/2011 - Initial Release

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Associated Answer Records

Answer Number	Answer Title	Version Found	Version Resolved
36174	Design Assistant for PCI Express - Start here for questions regarding Synthesis or Implementation	N/A	N/A

AR# 38625
Date	12/15/2012
Status	Active
Type	General Article
IP	Endpoint Block Plus Wrapper for PCI Express Virtex-6 FPGA Integrated Block for PCI Express ( PCIe ) Spartan-6 FPGA Integrated Endpoint Block for PCI Express ( PCIe )

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