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  3. AR# 3863: 3.1i CORE Generator - How do I generate Foundation functional simulation files for a VHDL design?
  4. AR# 38637: 12.3 Compxlib - "COMP96 ERROR COMP96_0196: "Expression must be locally static if the entity..."

AR# 38637

12.3 Compxlib - "COMP96 ERROR COMP96_0196: "Expression must be locally static if the entity..."

Description


I am using Aldec Riviera and would like to pre-compile the Xilinx simulation libraries. However, Compxlib displays an error when I compile the XilinxCoreLib library.The following error is shownin the Compxlib log file:
"COMP96 ERROR COMP96_0196: "Expression must be locally static if the entityname list denotes an entity interface, architecture body or configuration declaration."
"/tools/eda/Xilinx/12.3/ISE_DS/ISE/vhdl/src/XilinxCoreLib/glb_srl_fifo_v1_0.vhd" 288 56
How can I resolve this error?

Solution

This is a known issue with sources from the AXI interface.It is currently under investigation and is to be fixed in a future release of the ISE Design Suite tools.

To work around this issue, the -relax switch for theAldec Riviera Pro vcom command must be employed.This can be done by adding the switch to theOPTION line for Aldec in the Compxlib configuration file (compxlib.cfg).
For example:
#///////////////////////////////////////////////////////////////////////
# Setup file name: Aldec
SET:riviera:LIBRARY=library.cfg
#
# Aldec options for VHDL Libraries
# Syntax:-
# OPTION:<simulator_name>:<language>:<library>:<options>
# <library> :- u (unisim) s (simprim) c (xilinxcorelib)
# r (coolrunner)
# vcom -work <library> <OPTION> <file_name>
#
OPTION:riviera:vhdl:u:-93 -relax -quiet -nowarn ELAB1_0026
OPTION:riviera:vhdl:s:-93 -relax -quiet -nowarn ELAB1_0026
OPTION:riviera:vhdl:c:-93 -relax -quiet -nowarn ELAB1_0026
OPTION:riviera:vhdl:r:-93 -relax -quiet -nowarn ELAB1_0026
OPTION:riviera:vhdl:i:-93 -relax -quiet -nowarn ELAB1_0026
OPTION:riviera:vhdl:e:-93 -relax -quiet -nowarn ELAB1_0026

The "compxlib.cfg" fileshould be found in the directory where Compxlib was run.

For more information, see the Synthesis and Verification Design Guide .
AR# 38637
Date 12/15/2012
Status Active
Type General Article
Tools