When I run the Virtex-6 Broadcast Connectivity Kit Targeted Reference Designs (from XAPP1075), I encounter the following problems:
CRC errors for Quad SDI TX/RX demo
TX Rate / 1.001 appears to have no affect when toggling control from the ChipScope software
RX CRC errors reported during SDI Mode 0 (HD-SDI) and SDI Mode 2 (3G-SDI)
I do not see these CRC errors when I run the same reference designs on a Broadcast Connectivity Kit with ES silicon, but only on the kit with production silicon.
What is the problem and how can it be resolved?
An updated design is available.
A known issue exists with the Broadcast Connectivity Kit Targeted Reference Designs on ML605 Production Silicon boards. For instructions on how to check if you have an ML605 board with production silicon, see (Xilinx Answer 37579).
If you do have production silicon, then the following information applies:
ML605 Development Boards with ES silicon have the System ACE clock running at 32.000 MHz. Due to a BOM change, the System ACE clock frequency on the ML605 Development Boards with production silicon is now running at 33.000 MHz. As a result, ML605 Development Boards with production silicon onboard see the bit rate detector forcing the CDR to reset due to the difference in clock frequency, and the CDR is trying to re-acquire lock which causes RX CRC errors.
Additionally, when the bit rate detection unit uses a reference clock that is faster than it expects, it always reports the RXRECCLK as running slowly. As a result, the received bit rate is always reported as being /1.001.
Fix made to the design delivered above:
The resolution for this issue was to change the reference clock source for the SDI demos. The demo files have been regenerated using the 27 MHz clock generated from the FMC card (rather than the System ACE clock). These files have been tested on ML605 boards with both C (Production) and CES (ES) silicon. The updated design runs without problems in both HD-SDI and 3G-SDI modes. The reference design files have been regenerated and updated on the Virtex-6 Broadcast Connectivity Kit page: http://www.xilinx.com/support/documentation/virtex-6_broadcast_connectivity_kit.htm.
When running the Virtex-6 Broadcast Connectivity Kit Targeted Reference Designs, please ensure that you download the most recent version of the reference designs from the kit page.
Please note that this is an issue with the SDI demos for the BCK, caused by an ML605 Build of Materials change. Customers who are using the SDI core on their own hardware are not affected by this issue.