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  3. AR# 38717: Spartan-6 Integrated Block for PCI Express - Minimum sys_reset assertion length to properly reset the core

AR# 38717

Spartan-6 Integrated Block for PCI Express - Minimum sys_reset assertion length to properly reset the core

Description

Version Found: 1.1; v2.1
Version Resolved and other Known Issues: See (Xilinx Answer 45702).

The Spartan-6 FPGA Integrated Block Wrapper for PCI Express Wrapper core does not document how long to assert sys_reset.

Solution

sys_reset is an asynchronous reset that needs to be asserted a minimum of 1500 ns to properly reset the core.

Revision History
01/18/2012 - Updated; added reference to 45072
12/24/2010 - Updated for v2.2
10/26/2010 - Initial Release

Note: "Version Found" refers to the version the problem was first discovered. The problem might also exist in earlier versions, but no specific testing has been performed to verify earlier versions.

Linked Answer Records

Master Answer Records

Answer Number Answer Title Version Found Version Resolved
37939 Spartan-6 FPGA Integrated Block Wrapper for PCI Express (AXI) - Resolved issues in v2.1 N/A N/A
39371 Spartan-6 FPGA Integrated Block Wrapper for PCI Express (AXI) - Resolved issues in v2.2 N/A N/A
37938 Spartan-6 FPGA Integrated Block Wrapper v1.4 for PCI Express - Release Notes and Known Issues N/A N/A

Associated Answer Records

Answer Number Answer Title Version Found Version Resolved
45702 Spartan-6 FPGA Integrated Block for PCI Express - Release Notes and Known Issues for all AXI Interface versions N/A N/A
AR# 38717
Date 05/20/2012
Status Active
Type Known Issues
IP
  • Spartan-6 FPGA Integrated Endpoint Block for PCI Express ( PCIe )
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