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  3. AR# 38731: MIG v3.5-v3.91, Virtex-6 DDR3 - Simulation - 'SKIP' Calibration Causes Errors in the Example Design

AR# 38731

MIG v3.5-v3.91, Virtex-6 DDR3 - Simulation - 'SKIP' Calibration Causes Errors in the Example Design

Description

In Virtex-6 MIG DDR3  v3.5-91, when you select the parameter SIM_BYPASS_INIT_CAL = "FAST", it speeds up the simulation of the Example Design and it calibrates error free.

However when you select SIM_BYPASS_INIT_CAL = "SKIP", an error is received and simulation stops.

Solution

When you select SIM_BYPASS_INIT_CAL = "SKIP", bit alignment errors can occur in the PHY.

As a result the data valid signal is incorrectly asserted with a latency of one clock cycle.

This is scheduled to be fixed in the 14.2 release,  until then ensure that you set the SIM_BYPASS_INIT_CAL parameter to "FAST".

Linked Answer Records

Master Answer Records

Answer Number Answer Title Version Found Version Resolved
39128 MIG Virtex-6 and Spartan-6 v3.7 - Release Notes and Known Issues for ISE Design Suite 13.1 N/A N/A
50642 MIG Virtex-6 and Spartan-6 v3.92 - Release Notes and Known Issues for ISE Design Suite 14.3 N/A N/A

Associated Answer Records

Answer Number Answer Title Version Found Version Resolved
43130 MIG Virtex-6 and Spartan-6 v3.9 - Release Notes and Known Issues for ISE Design Suite 13.3 N/A N/A
41347 MIG Virtex-6 and Spartan-6 v3.8 - Release Notes and Known Issues for ISE Design Suite 13.2 N/A N/A
39128 MIG Virtex-6 and Spartan-6 v3.7 - Release Notes and Known Issues for ISE Design Suite 13.1 N/A N/A
38951 MIG v3.61 - Release Notes and Known Issues for ISE Design Suite 12.4-14.2 N/A N/A
37173 MIG v3.6 - Release Notes and Known Issues for ISE Design Suite 12.3 N/A N/A
45194 MIG Virtex-6 and Spartan-6 v3.91 - Release Notes and Known Issues for ISE Design Suite 13.4 N/A N/A
AR# 38731
Date 08/20/2014
Status Active
Type Known Issues
Devices
  • Virtex-6 CXT
  • Virtex-6 HXT
  • Virtex-6 LX
  • More
  • Virtex-6 LXT
  • Virtex-6 SXT
  • Less
IP
  • MIG