The OUT_TERM is supported for simulation in IBIS. However, not all models are available. The Spartan-6 FPGA Hspice models can be used to simulate all the OUT_TERM. The OUT_TERM models are names OT25/50/75 in the IBIS models. OUT_TERM overrides the SLEW and DRIVE attributes for LVCMOS and LVTTL, and SLEW for the HTSLand SSTL type standards.
If IBIS simulation is required where the model is missing from the IBIS models,you can work around this by using an equivalent IOSTANDARD.
Also SSTL15 and SSTL18 with OT25/50/75 can be used to model all the 1.5V and 1.8V OT outputs. For example, both HSTL_I_LR_25 and LVCMOS15_LR_25 with OUT_TERM = UNTUNED_50 could be modeledusing the SSTL15_OT50_LR_25 model. Similarly, SSTL18_OT50 could model HSTL_I_18 or LVCMOS18 with OUT_TERM=UNTUNED_50.This will give a close match to the line and approximate the OUT_TERM behavior.
Fordifferential versions of HSTL and SSTL,for exampleDIFF_HSTL, the OT can be modeled with two separate single-ended versions.