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Virtex-6 Integrated Block Wrapper v1.6 for PCI Express - Corrections for UG517
This answer record list corrections for the Virtex-6 Integrated Block Users Guide (UG517).
Version Dated September 21, 2010
Page 108: Figure 6-14 - Wave form for trn_rbar_hit_n is incorrect:trn_rbar_hit_n should beasserted throughout the packet from trn_rsof_n to trn_reof_n.
Page 121: Figure 6-29 - Labeling for trn_teof_n is incorrect: trn_eof_n should be "trn_teof_n".
Page 122: Text above Figure 6-30 states: "it also places a value of 01b on trn_trem_n[1:0]." Thevalue should be"10b".
Page 122: Figure 6-31 - On the trn_teof_n cycle, all 4 DWORDS are valid because trn_trem_n[1:0] = 00. The trn_td[127:0] entry should read "D1, D2, D3, D4".
Page 203: Table 7-2 - Footnote 3 should be applied to the HX565T-FF1923 entry for the X0Y1 block. A x8 link is not supported with X0Y1 for this device and package combination.
01/04/2011 - Added page 203 entry.
11/01/2010 - Initial Release
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- Virtex-6 CXT
- Virtex-6 HXT
- Virtex-6 LX
- Virtex-6 LXT
- Virtex-6 SXT
- Virtex-6 FPGA Integrated Block for PCI Express ( PCIe )