UPGRADE YOUR BROWSER

We have detected your current browser version is not the latest one. Xilinx.com uses the latest web technologies to bring you the best online experience possible. Please upgrade to a Xilinx.com supported browser:Chrome, Firefox, Internet Explorer 11, Safari. Thank you!
Page Bookmarked
  1. Xilinx - All Programmable
  2. Support
  3. AR# 38850: SPI-3 Link Layer v7.2 - Data mismatch between rdat and rx_data in Spartan-6 and Virtex-6

AR# 38850

SPI-3 Link Layer v7.2 - Data mismatch between rdat and rx_data in Spartan-6 and Virtex-6

Description

When targeting Spartan-6 or Virtex-6 FPGA using the SPI-3 Link Layer v7.2 core or earlier version, corruption is seen on the rx data path and the rx_data output is incorrect.

Solution

This issue has been fixed in v7.2rev1 of the core, available as a patch for download at (Xilinx Answer 35141).
AR# 38850
Date 05/23/2014
Status Archive
Type General Article
Devices
  • Virtex-6 LX
  • Virtex-6 LXT
  • Virtex-6 SXT
  • More
  • Spartan-6 LX
  • Spartan-6 LXT
  • Less
Tools
  • ISE Design Suite - 12.1
  • ISE Design Suite - 12.2
  • ISE Design Suite - 12.3
IP
  • SPI-3 Link Layer Interface, Multi-channel