We have detected your current browser version is not the latest one. Xilinx.com uses the latest web technologies to bring you the best online experience possible. Please upgrade to a Xilinx.com supported browser:Chrome, Firefox, Internet Explorer 11, Safari. Thank you!

AR# 38851

SPI-3 Link Layer v7.2 - Example design simulation testbench monitoring logic not connected


In v7.2 of the SPI-3 Link Layer core, the monitoring logic is not connected up in the simulation testbench. The monitoring logic checks that the data input to the rx interface matches the loopedback tx data available at the output. This affects all supported device families.


This issue has been fixed in v7.2rev1 of the core available as a patch for download; see (Xilinx Answer 35141).
AR# 38851
Date 05/23/2014
Status Archive
Type General Article
  • SPI-3 Link Layer Interface, Multi-channel
Page Bookmarked