AR# 38851: SPI-3 Link Layer v7.2 - Example design simulation testbench monitoring logic not connected
SPI-3 Link Layer v7.2 - Example design simulation testbench monitoring logic not connected
In v7.2 of the SPI-3 Link Layer core, the monitoring logic is not connected up in the simulation testbench. The monitoring logic checks that the data input to the rx interface matches the loopedback tx data available at the output. This affects all supported device families.
This issue has been fixed in v7.2rev1 of the core available as a patch for download; see (Xilinx Answer 35141).