UPGRADE YOUR BROWSER

We have detected your current browser version is not the latest one. Xilinx.com uses the latest web technologies to bring you the best online experience possible. Please upgrade to a Xilinx.com supported browser:Chrome, Firefox, Internet Explorer 11, Safari. Thank you!
Page Bookmarked
  1. Xilinx - All Programmable
  2. Support
  3. AR# 38852: SPI-3 Link Layer v7.2 - Demo testbench data dropped during simulation

AR# 38852

SPI-3 Link Layer v7.2 - Demo testbench data dropped during simulation

Description

If I target Virtex-6 devices, the example design testbench sometimes starts to send data before the MMCM has locked. This results in the data being dropped.

Solution

This issue has been fixed in v7.2 rev1 of the core available as a patch for download, see (Xilinx Answer 35141).

Linked Answer Records

Master Answer Records

Answer Number Answer Title Version Found Version Resolved
35141 SPI-3 Link Layer v7.2 - Release Notes and Known Issues for ISE Design Suite 12.1 N/A N/A
AR# 38852
Date 05/23/2014
Status Archive
Type General Article
Devices
  • Virtex-6 LX
  • Virtex-6 SXT
  • Virtex-6 LXT
IP
  • SPI-3 Link Layer Interface, Multi-channel