AR# 38865: PlanAhead 12.3 - PCIE_INTERNAL_1_1 primitive not recognized when loading Virtex-5 netlist design.
PlanAhead 12.3 - PCIE_INTERNAL_1_1 primitive not recognized when loading Virtex-5 netlist design.
When I load a Virtex-5 FPGA design with the PCIE core in PlanAhead 12.3, I get the following warning. "While importing this netlist, 1 undefined instance was found and converted to a black box. Make sure you have loaded all intended module defenitions before proceeding. Black boxes can be populated later by using Add Sources operation. Module name: PCIE_INTERNAL_1_" This warning did not occur in 12.2 and is a part of the PCIE core. Can I ignore this warning?
Yes, this warning can be ignored as NGDBuild still recognizes the primitive. If you want to constrain the PCIE primitive, you have to manually do this in the UCF (since PlanAhead is not currently recognizing the primitive type). This issue isto be fixed in a future release of PlanAhead.