Description

Solution

Following are some possible reasons:

• Check if DCI cascading is enabled; if yes, then only master bank should reserve the VRP/VRN pins, and the VRP/VRN pins on slave bank can be used as general purpose I/O.
• Check if Internal Vref is enabled; if yes, then Vref pins can be used as general purpose I/O.
• Check if the pins on that bank is used as output only; if yes, then DCI and Vref are not required. Details are described in the Virtex-6 FPGA SelectIO User Guide (UG361):http://www.xilinx.com/support/documentation/user_guides/ug361.pdf

Linked Answer Records

Associated Answer Records