AR# 38940


MIG v3.6 Virtex-6 QDRII+ - Import UCF does not import the clock signals.


When generating a new MIG v3.6 Virtex-6 FPGA QDRII+ design using the Fixed Pinout selection and the Import UCF feature, the clock signals may not be imported correctly and those valid pin locations may not be available to select.


If this occurs, select one of the available site locations and generate the design.

Then, open the *.ucf file that contains your generated pinout and manually change the clock pinout.

This is fixed in the ISE 13.1 MIG v3.7 software release.

Linked Answer Records

Associated Answer Records

Answer Number Answer Title Version Found Version Resolved
38951 MIG v3.61 - Release Notes and Known Issues for ISE Design Suite 12.4-14.2 N/A N/A
AR# 38940
Date 08/20/2014
Status Archive
Type General Article
Devices More Less
People Also Viewed