AR# 38951

MIG v3.61 - Release Notes and Known Issues for ISE Design Suite 12.4-14.2

Description

This Release Notes and Known Issues Answer Record is for the Memory Interface Generator (MIG) v3.61 released in ISE Design Suite 12.4 - 14.2 for Virtex-5 and older families. This answer record contains the following information:

  • General Information
  • Software Requirements
  • New Features
  • Resolved Issues
  • Known Issues

For installation instructions, general CORE Generator tool known issues, and design tools requirements, see the IP Release Notes Guide at:
http://www.xilinx.com/support/documentation/ip_documentation/xtp025.pdf

Solution

General Information

MIG v3.61 is available through ISE Design Suite 12.4-14.2.

For a list of supported memory interfaces and frequencies for Spartan-3 Generation, Virtex-4, and Virtex-5 FPGA, see the MIG User Guide
http://www.xilinx.com/support/documentation/ip_documentation/ug086.pdf

For a list of supported memory interfaces and frequencies for the Spartan-6 FPGA MCB, see the Spartan-6 FPGA Memory Controller User Guide
http://www.xilinx.com/support/documentation/user_guides/ug388.pdf

For a list of supported memory interfaces and frequencies for Virtex-6 FPGA, see the Virtex-6 FPGA Memory Interface Solutions User Guide and Data Sheet: 
http://www.xilinx.com/support/documentation/ip_documentation/ug406.pdf
http://www.xilinx.com/support/documentation/ip_documentation/ds186.pdf

Software Requirements 

  • Xilinx ISE Design Suite 12.4
  • Xilinx ISE Design Suite 13.1 - 14.2 for Virtex-5 and older families
  • Synopsys Synplify Pro D-2010.03 SP1 Support 
  • Synopsys Synplify Pro E-2011.03 Support
  • 32-bit/64-bit XP Professional
  • 32-bit/64-bit Vista Business (12.4 Only)
  • 32-bit/64-bit Windows Server 2008 (13.1 Only)
  • 32-bit/64-bit Linux Red Hat Enterprise 4.0
  • 32-bit/64-bit Linux Red Hat Enterprise 5.0
  • 32-bit/64-bit SUSE Linux Enterprise 11

New Features

  • ISE Design Suite 12.4 software support
  • ISE Design Suite 13.1-14.2 software support for Virtex-5 and older families
  • Updated MMCM settings for low frequencies

Resolved Issues
MIG User Guide

  • Provided trace length requirements for Q/CQ and D/K relationship for Virtex-6 QDR II+ SRAM designs in UG406
    • CR 564807
  • Provided an explanation as to how to modify the traffic generator for the CMD_PATTERN in UG416
    • CR 558915
  • Provided notes on how to drive IDELAYCTRL with a PLL in UG406
    • CR 566497
  • Provided more information on Class selection for various families (Spartan-3, Virtex-4, and Virtex-5) in UG086
    • CR 565600 and CR 566503

Known Issues
(Xilinx Answer 51293) MIG v3.61 fails to open in CoreGen because of missing mig.exe file in ISE 14.2

Virtex-6 MIG Designs
(Xilinx Answer 37968) MIG v3.6 Virtex-6 DDR2/DDR3 - Additional calibration stage (CLKDIV Calibration Stage) added to calibrate the timing of the BUFIO to BUFR transfer
(Xilinx Answer 37861) MIG v3.6, Virtex-6 DDR3 - Multi-Controller VHDL designs may exhibit data errors in simulation when targeting an RDIMM 
(Xilinx Answer 37863) MIG v3.6, Virtex-6 Multi-Controller - Default bank selection for all FF1760 packages results in MAP error 
(Xilinx Answer 37997) MIG v3.6 Virtex-6 DDR3 Multi-Controller - GUI only allows single controller generation for CXT -1 devices 
(Xilinx Answer 38083) MIG v3.6, Virtex-6 DDR3 - Multi-Controller Verilog designs are failing in simulation when targeting a UDIMM whose base part is x16
(Xilinx Answer 38104) MIG v3.6, Virtex-6 - GUI does not allow AXI RDIMM data width selection.
(Xilinx Answer 38111) Design Notes include incorrect statements regarding rank support and hardware testbench support.
(Xilinx Answer 38125) MIG v3.6, Virtex-6 DDR2/DDR3 - MIG v3.6, Virtex-6 DDR2/DDR3 - comments in the UCF are incorrect.
(Xilinx Answer 33440) MIG v3.2-3.6 Virtex-6 DDR2  - When ODT is disabled (RTT_NOM = 0), ODT is incorrectly asserted immediately following calibration.
(Xilinx Answer 38568) MIG v3.3-3.6, Virtex-6 DDR2/DDR3 - CK[0] and CK#[0] do not have to be placed at CC pins.
(Xilinx Answer 38939) MIG v3.6 Virtex-6 DDR3 - Debug signals to decrement Phase Detector IODELAY taps is wired incorrectly.
(Xilinx Answer 38940) MIG v3.6 Virtex-6 QDRII+ - Import UCF does not import clock signals.

Spartan-6 FPGA MCB
(Xilinx Answer 36550) MIG v3.5, Spartan-6 MCB - Synplify fails on a MIG output design 
(Xilinx Answer 38000) MIG v3.6 Spartan-6 MCB - WARNING:sim - ProjectMgmt - Circular Reference: work:Module|mux
(Xilinx Answer 38696) MIG Spartan-6 - Use of FPGA Suspend Mode and Self-Refresh Resets MCB
(Xilinx Answer 38651) MIG 3.6 Spartan-6 - DDR termination recommendation
(Xilinx Answer 38524) MIG Spartan-6 - Debug signals are only added to first port in the user interface
(Xilinx Answer 38623) MIG Spartan-6 MCB - Why is ODT issued late by the MCB when operating in DDR2 mode 400 Mbps?

Virtex-5 MIG Designs
(Xilinx Answer 50858) MIG Virtex-5 DDR2 Dual Rank - Incorrect Pre-charge issued when switching ranks causing data errors
(Xilinx Answer 41923) MIG v3.61 Virtex-5 DDR2 - MT47H512M8 generates incorrect COL_WIDTH

Spartan-3 Generation MIG Designs 
(Xilinx Answer 38105) MIG v3.3, Spartan-3A DDR2 - Failed MAXDELAY constraint on "dqs_int_delay_in" net for XC3S400a-FT256 devices
(Xilinx Answer 44811) MIG v3.61 Spartan-3E DDR - Example/user design warnings when verifying UCF

Linked Answer Records

Child Answer Records

Associated Answer Records

Answer Number Answer Title Version Found Version Resolved
44811 MIG 3.61 Spartan-3E DDR - Example/user design warnings when verifying UCF N/A N/A
41923 MIG v3.61 Virtex-5 DDR2 - MT47H512M8 generates incorrect COL_WIDTH N/A N/A
37861 MIG v3.6-v3.61 Virtex-6 DDR3 - Multi-Controller VHDL designs can exhibit data errors in simulation when targeting an RDIMM N/A N/A
37863 MIG v3.6-v3.7, Virtex-6 Multi-Controller - Default bank selection for all FF1760 packages results in MAP error N/A N/A
38000 MIG v3.6-v3.7 Spartan-6 MCB - WARNING:sim - ProjectMgmt - Circular Reference: work:Module|mux N/A N/A
37997 MIG v3.6-v3.61 Virtex-6 DDR3 Multi-Controller - GUI only allows single controller generation for CXT -1 devices N/A N/A
38083 MIG v3.6-v3.61, Virtex-6 DDR3 - Multi-Controller Verilog designs are failing in simulation when targeting a UDIMM whose base part is x16 N/A N/A
38104 MIG v3.6-v3.7, Virtex-6 DDR3 - The GUI does not allow AXI RDIMM data width selection N/A N/A
38105 MIG v3.3, Spartan-3A DDR2 - Failed MAXDELAY constraint on "dqs_int_delay_in" net for XC3S400a-FT256 devices N/A N/A
38111 MIG v3.6-v3.61 Virtex-6 DDR2/DDR3 - The Design Notes include incorrect statements regarding rank support and hardware testbench support N/A N/A
38125 MIG v3.6, Virtex-6 DDR2/DDR3 - Comments in the UCF are incorrect N/A N/A
33440 MIG v3.2-3.61 Virtex-6 DDR2 - When ODT is disabled (RTT_NOM = 0), ODT is incorrectly asserted immediately following calibration N/A N/A
38568 MIG v3.3-3.61 Virtex-6 DDR2/DDR3 - CK[0] and CK#[0] do not have to be placed at CC pins N/A N/A
38939 MIG v3.6-v3.61 Virtex-6 DDR3 - Debug signals to decrement Phase Detector IODELAY taps is wired incorrectly N/A N/A
38940 MIG v3.6 Virtex-6 QDRII+ - Import UCF does not import the clock signals. N/A N/A
38651 MIG 3.6 Spartan-6 - DDR termination recommendation N/A N/A
38524 MIG Spartan-6 - Debug signals are only added to first port in the user interface N/A N/A
38623 MIG Spartan-6 MCB - Why is ODT issued late by the MCB when operating in DDR2 mode 400 Mbps? N/A N/A
38132 Virtex-6 FPGA MMCM Design Advisory - MMCM BANDWIDTH attribute requirement N/A N/A
38731 MIG v3.5-v3.91, Virtex-6 DDR3 - Simulation - 'SKIP' Calibration Causes Errors in the Example Design N/A N/A
AR# 38951
Date 08/19/2014
Status Active
Type Release Notes
IP