When I retarget a Virtex-5 design containing DCM2PLL to Virtex-6, I receive the following errors:
How can I resolve these errors?
These errors indicate that the tool has problems retargeting the V5 DCM/PLL to V6 MMCM.
It is recommended to redesign and regenerate the MMCM cores when you retarget the design from V5 to V6, because the tool may not be able to retarget them automatically.
Below are the explanations of the two errors:
In the V5 design, the PLL COMPENSATION attribute is set to "DCM2PLL" which is not supported in MMCM.
To resolve this error, change this value to "SYSTEM_SYNCHRONOUS" or "SOURCE_ SYNCHRONOUS".
Alternatively you can regenerate the MMCM core manually.
This error indicates that the FVCO of MMCM is out of range when the tool is trying to retarget the V5 DCM to V6 MMCM.
You will need to regenerate the V6 MMCM to have it correctly configured to generate the clocks you need.