AR# 39047: Virtex-5 GTX RocketIO - Instantiating an unused GTX to forward reference clocks
AR# 39047
Virtex-5 GTX RocketIO - Instantiating an unused GTX to forward reference clocks
Description
To properly forward a reference clock through an otherwise unused GTX, the GTX needs to be instantiated. This Answer Record presents a correct method for instantiating a GTX with minimal interconnect and impact on the user design, and provides an example Verilog instantiation. In 12.3 and later, this situation is accompanied by the following error message:
"ERROR:PhysDesignRules:2270"
It is possible to see this error if the reference clock pins were not tied to specific locations via the LOC constraint. The RocketIO Wizard automatically generates these constraints in the example design's UCF file and can be used as reference.
Solution
The GTX needs to be instantiated with 3 sets of ports connected: the TX serial pairs, the RX serial pairs, and the CLKIN port.
The serial pairs need to be connected to output ports in the top level of the design.
The CLKIN port needs to be connected to either the output of a BUFG or IBUFDS.
The local IBUFDS can be instantiated, or an adjacent IBUFDS being used in the design can be used.
TXPOWERDOWN[1:0] and RXPOWERDOWN{1:0] can be connected to 2'b11 to save power, but REFCLKPWRDNB needs to be connected to 1'b1 to keep the reference clock routing powered.
The instantiation below has been tested to function in this regard: