AR# 39063

Spartan-6 FPGA Integrated Block for PCI Express - Why does trn_reset_n/user_reset_out(AXI) assert after sys_reset_n asserts?

Description

Version Found: v1.1; v2.1
Version Resolved and other Known Issues: See (Xilinx Answer 45702).

The Spartan-6 FPGA Integrated Block User Guide says trn_reset_n/user_reset_out(AXI) should be asserted at the same time as sys_reset_n. However, during simulation, at time zero when sys_reset_n is asserted, trn_reset_n/user_reset_out(AXI) does not assert for approximatelyfour microseconds (this also occurs in hardware).

Solution

This difference occurs only at startup (time 0) and is due to logic within the block that ensures no contention is on the outputs during configuration. After initial startup, any further assertions of sys_reset_n cause trn_reset_n/user_reset_out(AXI) to assert simultaneously. This behavior is expected.

Revision History
01/18/2012 - Updated; added reference to 45072
07/06/2011 - Updated for v2.3
12/11/2010 - Initial release

Note: "Version Found" refers to the version the problem was first discovered. The problem might also exist in earlier versions, but no specific testing has been performed to verify earlier versions.

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Linked Answer Records

Master Answer Records

Answer Number	Answer Title	Version Found	Version Resolved
37939	Spartan-6 FPGA Integrated Block Wrapper for PCI Express (AXI) - Resolved issues in v2.1	N/A	N/A

Associated Answer Records

Answer Number	Answer Title	Version Found	Version Resolved
45702	Spartan-6 FPGA Integrated Block for PCI Express - Release Notes and Known Issues for all AXI Interface versions	N/A	N/A
39371	Spartan-6 FPGA Integrated Block Wrapper for PCI Express (AXI) - Resolved issues in v2.2	N/A	N/A
37938	Spartan-6 FPGA Integrated Block Wrapper v1.4 for PCI Express - Release Notes and Known Issues	N/A	N/A
37939	Spartan-6 FPGA Integrated Block Wrapper for PCI Express (AXI) - Resolved issues in v2.1	N/A	N/A

AR# 39063
Date	12/15/2012
Status	Active
Type	General Article
Devices	Spartan-6 LXT
IP	Spartan-6 FPGA Integrated Endpoint Block for PCI Express ( PCIe )

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