Solution
General Information
MIG v3.7 is available through ISE Design Suite 13.1.
For a list of supported memory interfaces and frequencies for the Spartan-6 FPGA MCB, see the Spartan-6 FPGA Memory Controller User Guide and Memory Interface Solutions User Guide:
http://www.xilinx.com/support/documentation/user_guides/ug388.pdf
http://www.xilinx.com/support/documentation/ip_documentation/ug416.pdf
For a list of supported memory interfaces and frequencies for Virtex-6 FPGA, see the Virtex-6 FPGA Memory Interface Solutions User Guide and Data Sheet:
http://www.xilinx.com/support/documentation/ip_documentation/ug406.pdf
http://www.xilinx.com/support/documentation/ip_documentation/ds186.pdf
For general design and troubleshooting information on MIG, please refer to the Xilinx MIG Solution Center at (Xilinx Answer 34243) information regarding MIG cores for other FPGAs, see the IP Release Notes Guide to locate the appropriate MIG Release Notes and Known Issues Answer Record.
Software Requirements
- Xilinx ISE Design Suite 13.1
- Synopsys Synplify Pro E-2011.03 Support
- 32-bit/64-bit Windows AP Professional
- 32-bit/64-bit Windows 7 Professional
- 32-bit/64-bit Windows Server 2008
- 32-bit/64-bit Linux Red Hat Enterprise 4.0
- 32-bit/64-bit Linux Red Hat Enterprise 5.0
- 32-bit/64-bit SUSE Linux Enterprise 11
New Features
- ISE Design Suite 13.1 software support
- Support of traffic generator for AXI4 slave interface of Virtex-6 DDR2/3 SDRAM designs
- Support of traffic generator for AXI4 slave interface of Spartan-6 designs
Resolved Issues
MIG User Guide
- UG406: Uses phy_init_done in the UI signal description instead of dfi_init_complete
- UG406: Provided more details on clocks used in design
- UG416: Added more information on how to find the simulation-only debug signals
- UG406: Removed description related to CK[0] and CK#[0] for Virtex-6 interfaces as differential P-N pair is enough for CK[0] and CK#[0] pins and it should not be CC pins
- UG406: Removed references to reserving VREF pin for all Virtex-6 interfaces as VREF pins are not reserved in current algorithm
- UG406: Provided information on debug ports dbg_inc_rd_fps and dbg_dec_rd_fps
- UG406: Notes about clock domain transfer points in ISERDES are elaborated
MIG Tool
- MIG calculation resolution changed to 1ps from 2 decimal points
- Fixed issue with reading UCF in Fixed pin out selection for system clock pins
- Provided an option in the GUI for Memory Address Mapping Selection for ROW_BANK_COLUMN and BANK_ROW_COLUMN
- Corrected notes in bank selection page description related to CK[0] and CK#[0] as these pins should go for differential P-N pair and it should not be CC pair
- In fixed pin out selection, DRC window is open while accessing the MIG main window.
- In fixed pin out selection, user is able to select the system control pins in the outer columns for Virtex-6 designs
Virtex-6 FPGA
- Fixed issues with Fixed Pin Out option (Import UCF) for DDR2 SDRAM
- Added support for new Samsung parts for QDRII+ SRAM design
- Fixed issues with user design simulations for DDR3 SDRAM and DDR2 SDRAM interfaces
- Fixed issues with x16 component designs tRC violation in simulation when # of banks is increased to greater than 4 for DDR3 SDRAM and DDR2 SDRAM interfaces
- Verified the UCF which is generated using x4 component and provided the valid DQS_LOC_COLn and nDQS_COL parameters. As a result we will not have any unroutable situation for one or more connections
Spartan-6 FPGA
- self refresh mode does not exit correctly
- MCB Suspend is resetting MCB triggering a power-up re-calibration
- Verified whether the RZQ and ZIO sites are duplicated only when ZIO is required for the configuration
Known Issues
Virtex-6 FPGA MIG (Xilinx Answer 37863) MIG v3.6-v3.7, Virtex-6 Multi-Controller - Default bank selection for all FF1760 packages results in MAP error
(Xilinx Answer 38731) MIG v3.5-v3.8, Virtex-6 DDR3 - Simulation - 'SKIP' calibration causes errors in the Example Design
(Xilinx Answer 40468) MIG v3.7 Virtex-6 AXI - Verify UCF and Update Design and UCF does not work properly with MIG v3.61 designs
(Xilinx Answer 41768) MIG v3.7 Virtex-6 DDR2/DDR3 - AXI simulations fail during compilation when using ISE Simulator
(Xilinx Answer 42195) MIG v3.7 Virtex-6 DDR2/DDR3 - For ECC enabled designs, app_correct_en is not driven properly and ECC is not working
(Xilinx Answer 42198) MIG v3.7 Virtex-6 DDR2/DDR3 - For ECC enabled designs, app_wdf_mask is not driven properly
(Xilinx Answer 42233) MIG v3.7-v3.8 Virtex-6 RLDRAM II - Address Width does not change when using Address Multiplexing
(Xilinx Answer 41653) MIG v3.7-v3.8 Virtex-6 DDR3 - Traffic Generator address data masking is inconsistent in cmd_gen.vhd
(Xilinx Answer 41608) MIG v3.7 Virtex-6 DDR3 - "app_wdf_wren" stays low even though the write data FIFO should be ready
(Xilinx Answer 40741) MIG v3.61-v3.7 Virtex-6 QDRII+ - "WARNING:PhysDesignRules:2282 - Invalid configuration (incorrect pin connections and/or modes) on block..."
(Xilinx Answer 39423) MIG v3.61-v3.8 Virtex-6 DDR2/DDR3/QDRII+ - The VRN/VRP pins were occupied by controller I/Os which requires another bank for DCI Cascade
(Xilinx Answer 41918) MIG v3.7-v3.8 Virtex-6 DDR2/DDR3 - Traffic Generator does not simulate other data or command patterns
(Xilinx Answer 41652) MIG v3.7-v3.8 Virtex-6 DDR3 Traffic Generator error_status does not latch correct data
Spartan-6 FPGA
(Xilinx Answer 36550) MIG v3.5, Spartan-6 MCB - Synplify fails on a MIG output design with error "port LOCKED does not exist"
(Xilinx Answer 38000) MIG v3.6 Spartan-6 MCB - WARNING:sim - ProjectMgmt - Circular Reference: work:Module|mux
(Xilinx Answer 38623) MIG Spartan-6 MCB - Why is ODT issued late b the MCB when operating in DDR2 mode 400 Mbps?
(Xilinx Answer 40385) MIG Spartan-6 MCB - Timing violation on clock domain crossing when user interface clock and calibration clock have an odd ratio
(Xilinx Answer 40557) MIG v3.7 Spartan-6 MCB - Multi-controller example designs might not connect up all user logic clocks
Revision History
6/8/2011 - Added Known Issue Answer Record 41653
6/8/2011 - Added Known Issue Answer Record 41608
6/8/2011 - Added Known Issue Answer Record 41444
6/8/2011 - Added Known Issue Answer Record 40741
6/8/2011 - Added Known Issue Answer Record 39423
6/16/2011 - Added Known Issue Answer Record 41965
6/16/2011 - Added Known Issue Answer Record 41652
6/16/2011 - Added Known Issue Answer Record 41918
6/16/2011 - Added Known Issue Answer Record 35750