We have detected your current browser version is not the latest one. Xilinx.com uses the latest web technologies to bring you the best online experience possible. Please upgrade to a Xilinx.com supported browser:Chrome, Firefox, Internet Explorer 11, Safari. Thank you!

AR# 39160

12.3 Place: Error:1164 DCM - Clock Source Components placed too far away from each other


I am receiving errors from Place similar to the following when the design contains 1 or more DCMs in series:

ERROR:Place:1164 - The clock source component "DCM_INST1/DCM_SP" and a load component "clkgen.I0/U1_CLK2X_BUFG_INST" have been
constrained or locked on two locations that are too far from each other, which will cause the clock signal to be unroutable. In order to generate a placed
NCD that can be evaluated in FPGA Editor, please set the environment variable XIL_PLACE_DISABLE_MMCM_CLOCK_CHECK to 1


This issue can be fixed by LOC'ing the DCMs and the BUFGs in the same half of the device to allow for routing.
AR# 39160
Date 03/10/2015
Status Active
Type General Article
  • ISE Design Suite - 12.3