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For cases where this core has been integrated into your design, follow the instructions as described in the error message and linked Answer Records above. However, when implementing the example design as provided by the CORE Generator tool, the following modifications to the example UCF file are sufficient to avoid the error:
For xc5vlx and xq5vlx parts:
Change INST "MGTCLK_N" LOC = "Y3" to LOC = INST "MGTCLK_N" LOC = "AF3"
Change INST "MGTCLK_P" LOC = "Y4" to LOC = INST "MGTCLK_N" LOC = "AF4"
For xc5vsx parts:
Change INST "MGTCLK_N" LOC = "P3" to LOC = INST "MGTCLK_N" LOC = "Y3"
Change INST "MGTCLK_P" LOC = "P4" to LOC = INST "MGTCLK_N" LOC = "Y4"
For xq5vsx parts:
Change INST "MGTCLK_N" LOC = "P3" to LOC = INST "MGTCLK_N" LOC = "AF3"
Change INST "MGTCLK_P" LOC = "P4" to LOC = INST "MGTCLK_N" LOC = "AF4"
This issue is resolved in the Virtex-5 FPGA Embedded Tri-mode Ethernet MAC Wrapper v1.8 available in ISE 13.1.
AR# 39190 | |
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Date | 02/15/2011 |
Status | Active |
Type | General Article |
Devices |
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IP |
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