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AR# 39276

LogicCORE IP Peak Cancellation CFR (PC-CFR) v2.0 - Why does the PC_CFR not function correctly when I use ISE tools 12.2, 12.3, or 12.4?


When I generate the core with CORE Generator12.3 anduse the corresponding HDL simulation file for simulation, the output is not correct. The output signal is not clipped and seems to be a delayed version of the input. However, if I use the HDL simulation filefrom 12.1, the core functions correctly.


This problem has been traced to XST and how it creates the unisim and simprim models.So, this is an issue for ISE 12.2 , 12.3 or 12.4 software, verilogor VHDL, unisimor simprim models. The netlist also shows incorrect operation. This can be recognized by the fact that the output is a delayed version of the input data.

To work around this issue, generate the core in v12.1, and use the simulation models and the netlist.

For a detailed list of LogiCORE IP Peak Cancelation Crest Factor Reduction - Release Notes and Known Issues, see (Xilinx Answer 33760).

Linked Answer Records

Master Answer Records

Answer Number Answer Title Version Found Version Resolved
33760 LogiCORE IP Peak Cancellation CFR(PC-CFR) - Release Notes and Known Issues N/A N/A
AR# 39276
Date 12/15/2012
Status Active
Type General Article
  • Virtex-6 CXT
  • Virtex-6 HXT
  • Virtex-6 LX
  • More
  • Virtex-6 LXT
  • Virtex-6 SXT
  • Virtex-6Q
  • Less
  • ISE Design Suite - 12.1
  • ISE Design Suite - 12.2
  • ISE Design Suite - 12.3
  • ISE Design Suite - 12.4
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