This problem has been traced to XST and how it creates the unisim and simprim models.So, this is an issue for ISE 12.2 , 12.3 or 12.4 software, verilogor VHDL, unisimor simprim models. The netlist also shows incorrect operation. This can be recognized by the fact that the output is a delayed version of the input data.
To work around this issue, generate the core in v12.1, and use the simulation models and the netlist.
For a detailed list of LogiCORE IP Peak Cancelation Crest Factor Reduction - Release Notes and Known Issues, see (Xilinx Answer 33760).