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AR# 3928

Foundation F1.4 XVHDL: Using JTAG pins (TDI, TDO, TCK, TMS) for general I/O

Description


Urgency: Standard



General Description:



The JTAG pins may be used as general I/O after configuration

by instantiating the special JTAG pin components (TDI, TDO,

TCK, TMS) in your VHDL code. One thing to note, the pins have

different functionality based upon whether the jtag pins are used

after configuration. Each will be specified below. Also, this

functionality is only valid in the 4000E/X, Spartan, and 5200

families of FPGA's.

Solution


After configuration, if boundary scan is not used, the TMS, TCK, and TDI pads are unrestricted and can be used as user input/output pads.



After configuration, if boundary scan is not used, the TDO pad can be used as a bidirectional 3-state I/O pad.



Here is the sample code.



library IEEE;

use IEEE.std_logic_1164.all;



entity JTAG is



port ( d : out std_logic);



end JTAG;





architecture JTAG_arch of JTAG is





component TDO

port ( O : out std_logic);

end component;



component TDI -- This could also be changed to TMS.

port ( I : in std_logic);

end component;



component TCK

port ( I : out std_logic); --used as input pin

end component;



component IBUF

port ( I : in std_logic; O : out std_logic);

end component;



component OBUF

port ( I : in std_logic; O : out std_logic);

end component;



signal a,b,c,abuf,bbuf,cbuf : std_logic;



begin



U1: TDO port map ( O => abuf );

U2: IBUF port map ( I => abuf, O => a );

U3: TCK port map ( I => bbuf );

U4: IBUF port map ( I => bbuf, O => b );

U5: TDI port map ( I => cbuf );

U6: OBUF port map ( I => c, O => cbuf );



process(a,b)

begin

c <= a and b;

d <= a and b;

end process;



end JTAG_arch;



After configuration, if boundary scan is used, the TDO pad can

be configured as a user output. The TDI, TCK, and TMS pads

can be configured as user inputs.



Here is some sample code.



library IEEE;

use IEEE.std_logic_1164.all;



entity JTAG is



port ( d : out std_logic);



end JTAG;





architecture JTAG_arch of JTAG is





component TDI -- This can also be TMS

port ( I : out std_logic); -- Used as input pin.

end component;



component TDO -- This could also be changed to TMS.

port ( O : in std_logic); --used as output pin

end component;



component TCK

port ( I : out std_logic); --used as input pin

end component;



component IBUF

port ( I : in std_logic; O : out std_logic);

end component;



component OBUF

port ( I : in std_logic; O : out std_logic);

end component;



signal a,b,c,abuf,bbuf,cbuf : std_logic;



begin



U1: TDI port map ( I => abuf );

U2: IBUF port map ( I => abuf, O => a );

U3: TCK port map ( I => bbuf );

U4: IBUF port map ( I => bbuf, O => b );

U5: TDO port map ( O => cbuf );

U6: OBUF port map ( I => c, O => cbuf );



process(a,b)

begin

c <= a and b;

d <= a and b;

end process;



end JTAG_arch;
AR# 3928
Date Created 08/31/2007
Last Updated 04/16/2012
Status Archive
Type General Article