This issue can occur for some Spartan-6 and Virtex-6 FPGA designs, but not all. The".xise" project file is not updated with the process property.
<property xil_pn:name="Global Optimization map" xil_pn:value="Off" xil_pn:valueState="default"/>
Even if implementation is complete with "-global_opt speed", the process status icon displays as "out of date" after restarting the ISE tools.
This issue is resolved in ISE Design Suite 13.1.