The static timing analysis (STA) performs worst case timing analysis of IDELAY components based on the delay tap value specified in the RTL or netlist.
It can only model this behavior when IDELAY is used in fixed mode.
When IDELAY is working in variable mode, the delay tap is dynamically calibrated in real time.
The delay value is not predicable for STA and the STA result does not reflect the actual performance that can be achieved on the interface.
As a result, it is not necessary to use OFFSET IN to check the interface timing in this case.