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AR# 39331

System Monitor/XADC Design Assistant - Troubleshooting

Description

Note: This Answer Record is part of the Xilinx System Monitor and XADC Solution Center (Xilinx Answer 39323).

The Xilinx System Monitor and XADC Solution Center is available to address all questions related to System Monitor and XADC.

Whether you are starting a new design with Virtex-6 FPGA or troubleshooting a problem, use the System Monitor and XADC Solution Center to guide you to the right information.

Solution

The first step in debugging your System Monitor design is to determine if the issue is with the hardware or the design.

To determine this, use the System Monitor console in the ChipScope tool on a blank device.

When the device is blank, System Monitor is in safe mode which means that the System Monitor is in continuous sampling mode doing conversions on Temperature, Vccint, Vccaux, and calibration.

If the System Monitor is reading correct values on a blank device, then the issue is more than likely a design issue.

If the System Monitor is reading incorrect values on a blank device, then the issue is more than likely a hardware issue.

 

 

 

If you are finding a difference between the case temperature and the System Monitor reading, see the following answer records:


(Xilinx Answer 34302) System Monitor - The Temperature measured on the device package is different than that measured by the System Monitor
(Xilinx Answer 24431) Virtex-5/-6 System Monitor - Where on the die does System Monitor measure the temperature, and how is it measured?

If you are finding that the accuracy of your reading is not as expected, the probable source is the accuracy of your reference.

See the following answer records:

(Xilinx Answer 24512)LogiCORE System Monitor Wizard v1.0 - Release Notes and Known Issues for the System Monitor Wizard
(Xilinx Answer 33722) Virtex-5 FPGA System Monitor - Why was the ADR03 reference removed from User Guide?
(Xilinx Answer 36642) Virtex-6 System Monitor - Maximum DCLK frequency revised down to 80 MHz

If you are finding that the data read from the System Monitor is not changing, see (Xilinx Answer 30090) Virtex-5 System Monitor - DEN behavior in DRP.

If you are noticing an inaccuracy on external channels only but the on-chip sensors are accurate, see the following answer records:
 

(Xilinx Answer 35979)Virtex-6 System Monitor - VP/VN Input Sample Current

Other issues:

(Xilinx Answer 37882)Virtex-6 System Monitor - Explanation of AC impedance matching in Figure 26 of UG370
(Xilinx Answer 31930)Virtex-5 System Monitor - User Temperature alarm incorrectly asserted post configuration

 

Linked Answer Records

Master Answer Records

Answer Number Answer Title Version Found Version Resolved
39323 System Monitor/XADC - Solution Center N/A N/A

Associated Answer Records

Answer Number Answer Title Version Found Version Resolved
39327 Xilinx System Monitor/XADC Solution Center - Design Assistant N/A N/A
AR# 39331
Date Created 11/26/2010
Last Updated 06/09/2016
Status Active
Type General Article
Devices
  • Artix-7
  • Kintex-7
  • Virtex-5 FXT
  • More
  • Virtex-5 LX
  • Virtex-5 LXT
  • Virtex-5 SXT
  • Virtex-5 TXT
  • Virtex-5Q
  • Virtex-5QV
  • Virtex-6 HXT
  • Virtex-6 LX
  • Virtex-6 LXT
  • Virtex-6 SXT
  • Virtex-7
  • Less