Answer Number | Answer Title | Version Found | Version Resolved |
---|---|---|---|
45723 | Virtex-6 FPGA Integrated Block for PCI Express - Release Notes and Known Issues for all AXI Interface Versions | N/A | N/A |
Answer Number | Answer Title | Version Found | Version Resolved |
---|---|---|---|
40707 | Virtex-6 Integrated Blcok Wrapper v2.2 for PCI Express - Interrupt Status bit not set when generating Legacy Interrupt | N/A | N/A |
40637 | Virtex-6 FPGA Integrated Block for PCI Express - DRC Error During Simulation using Provided Root Port Model | N/A | N/A |
Answer Number | Answer Title | Version Found | Version Resolved |
---|---|---|---|
39656 | Viretx-6 FPGA Integrated Block for PCI Express - Clock net TxOutClk_bufg is not constrained | N/A | N/A |
39544 | Virtex-6 FPGA Integrated Block for PCI Express (AXI) - Asynchronous Links Should Change PMA_RX_CFG | N/A | N/A |
37784 | Virtex-6 FPGA Integrated Block for PCI Express - x8 Gen 2 Timing Closure | N/A | N/A |
34009 | Virtex-6 Integrated Block Wrapper for PCI Express- PCI Express link will not train on ML605 boards using ES silicon | N/A | N/A |