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AR# 39373

MIG v3.6 Virtex-5 QDRII - multi-controller design is unable to complete through the Fixed Pinout Pin Selection

Description

A MIG v3.6 Virtex-5 QDRII multi-controller design is unable to complete through the Fixed Pinout Pin Selection.

The Pin Selection for Controller 0 shows that two Master Banks and masterbank_sel_pin's should be selected, but if both are selected then validation fails with the following:

Validation:- As per selected memory configuration one master bank is required.


If you do not select the second Master Bank, then validation is successful and you can proceed to the Controller 1 Pin Selection page.

However, you now do not have the ability to select the Master Bank or masterbank_sel_pin and as a result validation fails with the following:

Validation:- Master Bank is required if data width is more than 18 and DCI Cascade is enabled.

Solution

To work around this issue and use a fixed pinout, you must perform the following:
 
  1. First generate a MIG design using the default pinout with the Banks Selected based on your fixed pinout selections. 
  2. Open the example_top.ucf to modify your the pin locations and master bank selections.  
  3. Open the MIG again and run through the "Verify UCF and Update Design and UCF" flow using the generated mig.prj and example_top.ucf that contains your fixed pinout.

Performing the above validates your pinout modifications and regenerates the MIG controller with your new pinout.
 
This issue is currently not scheduled to be fixed.
AR# 39373
Date Created 11/30/2010
Last Updated 07/28/2014
Status Active
Type General Article
Devices
  • Virtex-5 FXT
  • Virtex-5 LX
  • Virtex-5 LXT
  • More
  • Virtex-5 SXT
  • Virtex-5 TXT
  • Less
IP
  • MIG