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AR# 39380

Design Assistant for PCI Express - Receiver detect problems

Description

This Answer Record helps debug issues with receiver detect failing.

NOTE: This Answer Record is part of the Xilinx Solution Center for PCI Express(Xilinx Answer 34536).TheXilinx Solution Center for PCI Express is available to address all questions related to PCIe. Whether you are starting a new design with PCIe or troubleshooting a problem, use the Solution Center for PCIeto guide you to the right information.

Solution

Both link partners must perform receiver detect.For more information on how to successful verify the receiver detect operation,see (Xilinx Answer 39525).

Receiver detect is the first state of the Link Training Status State Machine (LTSSM). To pass this state, the link partner transmits a pulse on
its TX lanes and measures the impedance of the link partner's receive line. If the impedance is too high, then the there is no advance in LTSSM.For more details, please read through section 4.3.1.8 of the PCI Express Base Specification.

Todetermine whether the link partner has passed the detect state, check the transceiver's RXELECIDLE output. If this signal is asserted indefinitely, then this means that the link partner did not detect the the PCI Express core. If this happens, make sure to check the RCAL circuitry of the transceiver. If the RCAL circuitry is incorrect, this might affect the termination of the transceiver. Please refer to the transceiver user guide to ensure proper setup for the RCAL circuit.

To determine whether the core detects its link partner, take a look at the LTSSM signal from the core. If the LTSSM state of the core does not pass detect, then there is an issue with the link partner's termination, or it is a board related issue. Please refer to the documentation of the core to find the detect states within the ltssm signal; see(Xilinx Answer 35920). All PCI Express cores from Xilinx provide this signal.

Another reason receiver detect might failis because of animproper board layout, such as missing AC caps on the Transmit traces.For more information on proper board layout, see the user guide chapter entitled "Board Design Guidelines".

Revision History
03/09/2011 - Initial Release

Linked Answer Records

Associated Answer Records

Answer Number Answer Title Version Found Version Resolved
34085 Design Assistant for PCI Express - Hardware Debug N/A N/A
AR# 39380
Date Created 03/09/2011
Last Updated 01/27/2013
Status Active
Type General Article
IP
  • Endpoint Block Plus Wrapper for PCI Express
  • Virtex-6 FPGA Integrated Block for PCI Express ( PCIe )
  • Spartan-6 FPGA Integrated Endpoint Block for PCI Express ( PCIe )