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AR# 39391

Virtex6 GTX- TXRESET should be asserted after GTXTEST double reset


When reference clock is used generate TXUSRCLK and TXUSRCLK2, TX buffer overflows when GTXTEST[1] is asserted. Is this expected and what is the work-around?


The Virtex-6 GTX Transceivers User Guide (UG366) explains the requirement of resetting the TX output clock divider twice using the GTXTEST[1] port when the TX output clock divider TXPLL_DIVSEL_OUT is set to /2 or /4. Because of design requirements, there are cases where TXUSRCLK and TXUSRCLK2are generated directly from reference clock rather than from TXOUTCLK. Usersshould still be resetting the TX output clock divider twice using the GTXTEST[1] port. To see the TXBUFSTATUS going to 11 is expected and indicates anoverflow of the TX buffer during GTXTEST[1] assertion. It is recommended to toggle TXRESET at the end of the double resetting sequence in order to clear the TX buffer.
AR# 39391
Date 12/15/2012
Status Active
Type General Article
  • Virtex-6 LXT
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