You are using a deprecated Browser. Internet Explorer is no longer supported by Xilinx.
MIG v3.6-v3.91 Virtex-6 DDR2/DDR3/QDRII+ - The VRN/VRP pins were occupied by controller I/Os which require another bank for DCI Cascade
In some instances, MIG will place an I/O on VRN/VRP pins in a bank even if very few data signals are used on that bank and there are many other available I/O.
If Internal VREF is disabled, then this bank must be used as a Slave Bank for DCI Cascading, which can limit the bank usage for the remaining available I/O.
If this placement is not desired, you can generate the MIG design using the default pinout and manually modify the generated *.ucf constraint file.
Then, run the MIG generated mig.prj and the modified *.ucf through the "Verify UCF and Update Design and UCF" flow in the MIG GUI.
This will validate your pinout changes and regenerates the MIG design according to your new pinout.
For more details on when VRP/VRN can be used as GPIO, refer to (Xilinx Answer 38926).
This behavior is scheduled to be changed starting in ISE 14.1 software.
Was this Answer Record helpful?
Linked Answer Records
Master Answer Records
Child Answer Records
Associated Answer Records
- Virtex-6 CXT
- Virtex-6 HXT
- Virtex-6 LX
- Virtex-6 LXT
- Virtex-6 SXT