Starting with v2.3 (AXI) and v1.7 (Legacy TRN) released in ISE 13.1 software, the MMCM will be constrained for the user in the UCF file. Until those cores are released, the user should ensure the MMCM is placed in the correct region. There are two ways to ensure this occurs. The first is to use the "buffer_type" XST attribute on the clock net and set it to "none." The second is to use a UCF LOC constraint to force the MMCM to a pre-selected location. These locations can be determined via the Virtex-6 Package and Pinout Guide (UG365):
If users have modified the wrapper to add a BUFG to this path in order to move the MMCM out of the region with the MGTs, it must be removed and the MMCM should be located in the region with the MGT providing TXOUTCLK.
Making this modification has no impact on PCI Express lane-to-lane skew compliance. The solution remains compliant to the PCIe lane to lane skew requirements.
07/05/2011 - Updated title.
03/03/2011 - Updated note about ISE 13.1 cores containing fix.
02/18/2011 - Clarified the MMCM is in the same region as Lane 0; Added that MMCM will be constrained in UCF for future core versions.
01/21/2011 - Updated note.
01/17/2011 - Initial Release.