We have detected your current browser version is not the latest one. Xilinx.com uses the latest web technologies to bring you the best online experience possible. Please upgrade to a Xilinx.com supported browser:Chrome, Firefox, Internet Explorer 11, Safari. Thank you!

AR# 39459

12.4 EDK - My Base System Builder design fails timing on the SP605 board at 100 MHz


When I have an AXI system with the Ethernet core targeted at 100 MHz, my design fails timing. Is there a way to maintain the 100 MHz clock frequency?


In the UCF, comment out the following two lines:

# Data path timing depends on the destination clock period
TIMESPEC "TS_axistreamclks_2_axi4liteclks" = FROM axistream_clk TO axi4lite_clk 20000 ps DATAPATHONLY; #assumes axi4lite_clk <= 50 MHz
TIMESPEC "TS_axi4liteclks_2_axistreamclks" = FROM axi4lite_clk TO axistream_clk 6667 ps DATAPATHONLY; #assumes axistream_clk <= 150 MHz

Linked Answer Records

Master Answer Records

Answer Number Answer Title Version Found Version Resolved
34609 12.x EDK - Master Answer Record List N/A N/A
AR# 39459
Date 12/15/2012
Status Active
Type General Article
Boards & Kits
Page Bookmarked