We have detected your current browser version is not the latest one. Xilinx.com uses the latest web technologies to bring you the best online experience possible. Please upgrade to a Xilinx.com supported browser:Chrome, Firefox, Internet Explorer 11, Safari. Thank you!

AR# 39488

Design Assistant for PCI Express - Virtex-6 Integrated Block for PCI Express ChipScope Pro Templates


This Answer Record provides links to the Virtex-6 Integrated Block for PCI Express ChipScope Pro Templates.


ChipScope Pro is often needed when debugging various issues with the core. The following provides insertion templates that can be used to debug most common problems that customer's face. These flows use instantiations of ChipScope rather than using the ChipScope Inserter. This means youneedto modify the provided core wrapper files to insert ChipScope.

Link Training Debug
Download either the VHDL or Verilog version from the following links:

The ZIP files contain a "readme.txt" file with instructions on how to insert the ChipScopeILA core.

This ILA insertion includes many signals that cover a wide range of possible problems. The down side to this is that timing might be more difficult to meet in some cases. If possible, use the example design provided with the core as it is easier to meet timing with this larger insertion.

Open the "pcie_2_0_v6.v[hd]" file to insert this ChipScope instantiation. The instantiation is in the "readme.txt" file.Note that this is provided for a x8 core and uses roughly 65 block RAM and 428 data connections.If you have a smaller lane width, you can use this instantiation as is or you can comment out the upper lanes. Look for the comments in the code to identify what needs to be changed; if you do this, you need to also modify the ILA xco file to reduce the size of the data width for the generated ILA core. To do this, edit the "pipe_ila.xco" file and change the "data_port_width" parameter to be smaller.

A generated ILA and ICON core is not included by default. To generate the cores, type the following at the command line, or import the xco files into the CORE Generator tool. This way, the generated cores match the analyzer software version in use.

coregen -p coregen.cgp -b pipe_ila.xco
coregen -p coregen.cgp -b chipscope_icon.xco

Revision History

03/09/2011 - Initial Release

AR# 39488
Date 01/30/2013
Status Active
Type General Article
  • Virtex-6 CXT
  • Virtex-6 HXT
  • Virtex-6 LXT
  • Virtex-6 SXT
  • Virtex-6 FPGA Integrated Block for PCI Express ( PCIe )
Page Bookmarked