At the user interface, monitor for the deassertion of the user application interface resetsignals. For the legacy TRN interface, this means trn_reset_n will be high. For the AXI interface, user_reset_out will be asserted low.
Also, users can insert ChipScope Pro following (Xilinx Answer 39488) tomonitor the following signals:
If these signals are asserted, but trn_reset_n/user_reset_out is still not released, then see (Xilinx Answer 34894).
The figure below shows what the signals shouldlook like.Continue the debug steps in (Xilinx Answer 34151).
This figure shows all signals in their expected state (reset deasserted and clocks locked).
This figure shows what is expected at start up. The GTPLLLOCK will assert followed by the CLOCKLOCKED from the MMCM. It is expected that system reset can still be asserted low when this happens.