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  1. Xilinx - All Programmable
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  3. AR# 39533: 12.3 EDK, MPMC - Integrated MIG GUI flow only generates one clock enable for dual-rank SODIMMs

AR# 39533

12.3 EDK, MPMC - Integrated MIG GUI flow only generates one clock enable for dual-rank SODIMMs

Description

When I select a dual-rank SODIMM, such as MT8HTF12864HD-40E, in the MPMC configuration, the integrated MIG GUI flow does not generate a UCF with the desired 2 CE pins.

After MIG GUI flow, only one CE port is listed in the UCF in MIG directory.

Solution

As a work-around, either add the desired CE pin LOCation constraint to the top-level UCF file, or use the standalone MIG GUI flow. For details of standalone MIG GUI flow, refer to the MPMC data sheet.

This behavior is not currently planned to be fixed in the MPMC core.


AR# 39533
Date 12/15/2012
Status Active
Type General Article
Tools
  • EDK - 12.3
  • EDK - 12.4
  • EDK - 13.1
IP
  • Multi-Port Memory Controller (MPMC)