In timing simulation, using ISE software 12.2 and later for Virtex-6 FPGA devices, the testbench is applying the data on the xgmii interface before the rx clock out of the MMCM is locked. This results in the following error:
"ERROR: Receiver fail : RX_DATA incorrect"
To work around this error, the data needs to be delayed for 175 clock cycles minimum (125 is the actual number of clocks in original testbench).
If using VHDL in <core_name>/simulation/demo_tb.vhd starting on line 669 change:
for i in 1 to 125 loop
for i in 1 to 200 loop
If using Verilog in <core_name>/simulation/demo_tb.v starting on line 892 change:
for (I = 0; I < 125; I = I + 1)
for (I = 0; I < 200; I = I + 1)
This issue is to be resolved in the core testbench for the next release of the core.