When using the Virtex-6 FPGA Integrated Block for PCI Express, how can I check to see if the receiver is experiencing 8b10b or disparity errors?
Note: This Answer Record is a part of the Xilinx Solution Center for PCI Express(Xilinx Answer 34536). TheXilinx Solution Center for PCI Express is available to address all questions related to PCIe. Whether you are starting a new design with PCIe or troubleshooting a problem, use the Solution Center for PCIeto guide you to the right information.
Bad signal integrity can impact link training. This could be due to problems with the reference clock or the differential receive pair.
Users can insert ChipScope Pro analyzer following (Xilinx Answer 39488) tomonitor the following signals to determine if any errors are happening on the receiver:
The figures below show what to expect.Continue the debug steps in (Xilinx Answer 34151).
During normal operation once the link begins to train and throughout normal data transfers,PIPERX#STATUSGT, should be 000b. Other values (100b and 111b) indicate problems with the received data. This figure shows the link in L0 with normal activity and all zeroes onPIPERX#STATUSGT.
Before PIPERX#ELECIDLEGT goes low,PIPERX#STATUSGT has a value of 100b, but once data starts, it goes to 0 as shown in this figure.
If the link is having issues such as training down to lower lane widths or going through RECOVERY or a complete loss of link up, trigger onPIPERX#STATUSGT to find out if there are issues with the received data stream.
03/14/2011 - Fixed link to 39488
03/09/2011- Initial Release