AR# 39843

13.x EDK - Master Answer Record

Description

This Master Answer Record contains a list of all EDK 13.x Answer Records. The list contains current known issues as well as issues resolved in a particular release.

Solution

Known Issues in 13.4

Resolved Issues in 13.4


(Xilinx Answer 45108) 13.3 EDK - XPS hangs when I attempt to open a project
(Xilinx Answer 45171) 13.3 EDK, SDK - ld.exe: BFD 2.16 assertion fail
(Xilinx Answer 45281) 13.3 EDK, AXI_V6_DDRx - Lower memory throughput in EDK 13.3 only
(Xilinx Answer 43335) 13.2 EDK - Can I use Digilent Cables with SDK/XMD?
(Xilinx Answer 38174) 12.2 EDK, MPMC 6.01a - "WARNING:Route:436 - The router has detected an unroutable situation..."
(Xilinx Answer 40257) 13.1 EDK - GUI issues


Known Issues in 13.3


(Xilinx Answer 43967) 13.3 EDK - KC705 Base System Builder (BSB) Known Issues
(Xilinx Answer 44088) 13.3 EDK, AXI_V6_DDRx - External memory model simulations fail when using ECC
(Xilinx Answer 44703) 13.3 EDK, AXI_XADC - ADC B conversion returns '0' for channels VCCAUX9 (channel 25) and VCCAUX15 (channel 31) in simultaneous sampling mode
(Xilinx Answer 44579) 13.2 EDK, AXI_HWICAP Abort status is not captured and stored correctly
(Xilinx Answer 44578) 13.2 EDK, AXI_HWICAP - Data Read from AXI HWICAP Occurs One Clock Cycle too Early during Simulation


Resolved Issues in 13.3


(Xilinx Answer 44113) 13.2 EDK, axi_emc - KC705 Flash Does Not Function
(Xilinx Answer 43775) 13.2 EDK - Does AXI User logic master support length width greater than 12?
(Xilinx Answer 43457) 13.2 EDK, AXI_DMA - axidma_v4_00_a example 'xaxidma_example_simple_intr.c' is incorrect
(Xilinx Answer 43307) 13.2 EDK: _mh files Are Not Found in the EDK Install Directory
(Xilinx Answer 43383) 13.2 EDK - BSB Generated MHS parameters of AXI_V6_DDRx is incorrect for third party boards
(Xilinx Answer 42860) 13.2 EDK, AXI_Ethernet v3.00.a - Known Issues with v3.00.a of the core released with EDK 13.2
(Xilinx Answer 42778) 13.2 EDK, AXI_IIC - ACKs are missed when using non-zero INERTIAL_DELAYs
(Xilinx Answer 42412) 13.1 EDK, XPS_IIC - The driver example code does not flush the Tx FIFO when the protocol is abnormally terminated
(Xilinx Answer 42340) 13.2 EDK, BSB - "ERROR:EDK - No BUS_INTERFACE S_AXI found as specified for PARAMETER C_BASEADDR"
(Xilinx Answer 41376) 13.1 EDK - SIM_DEVICE generic does not include support for Spartan-6 FPGA
(Xilinx Answer 41254) 13.2 EDK - "ERROR:HDLCompiler:443 - "sysmon_adc_core.vhd" Line 250: Function int_to_string does not always return a value"
(Xilinx Answer 40302) 13.1 EDK, XPS or AXI USB2 Device ERROR:EDK - [axi/xps]_usb2_device_0 - can't use empty string as operand of "/"
(Xilinx Answer 40290) 12.4 EDK, XPS_USB2_Device_v5.00a - "ERROR:Xst:1672 - TIMEGRP 'TG_ulpi_0_clock_grp' already defined"
(Xilinx Answer 38389) 12.3 EDK - Interrupts cause multiple accesses to peripheral, corrupting data on PowerPC 440 designs


Known Issues in 13.2


(Xilinx Answer 41254) 13.2 EDK - ERROR:HDLCompiler:443 - "sysmon_adc_core.vhd" Line 250: Function int_to_string does not always return a value
(Xilinx Answer 42860) 13.2 EDK, AXI_Ethernet v3.00.a - Known issues with v3.00.a of the core released with EDK 13.2 (PENDING)
(Xilinx Answer 42906) 13.2 EDK, MPMC - Where is the MPMC v6.04.a change log?
(Xilinx Answer 42905) 13.2 EDK, AXI Interconnect - Cascaded Interconnects or ID masters do not simulate in ISIM
(Xilinx Answer 40500) 12.1 EDK - CIP Wizard does not generate Verilog examples
(Xilinx Answer 38127) 12.3 EDK - While running genace.tcl, I get the following Error: error renaming "executable.svf" to "C:/temp/executable.svf" permission denied
(Xilinx Answer 21533) 12.1 EDK - How do I reduce the size of the executable program (".elf" file)?
(Xilinx Answer 39491) 12.3 EDK - "ERROR:EDK - microblaze_0 (microblaze) - syntax error in expression "$value != 0.0": extra tokens at end of expression"
(Xilinx Answer 38592) 12.1 EDK - mb-gcc does not properly pack structures using bitfields


Resolved Issues in 13.2


(Xilinx Answer 40290) 12.4 EDK, XPS_USB2_Device_v5.00a - "ERROR:Xst:1672 - TIMEGRP 'TG_ulpi_0_clock_grp' already defined"
(Xilinx Answer 37634) 12.2 EDK, PPC440MC_DDR2 - WARNING:EDK - : Bit 8:9 of C_PPC440MC_CONTROL is set to 00
(Xilinx Answer 39456) Virtex-6 FPGA Integrated Block Wrapper for PCI Express - Delay Aligner Work-around
(Xilinx Answer 40302) 13.1 EDK, XPS or AXI USB2 Device ? ERROR:EDK - [axi/xps]_usb2_device_0 - can't use empty string as operand of "/"
(Xilinx Answer 39530) 12.3 EDK, xps_timer v1.02.a - Interrupt is not generated again after two timers output interrupt simultaneously
(Xilinx Answer 40206) 13.1 EDK, AXI_FIFO_MM_S - "ERROR:PhysDesignRules - Issue with pin connections and/or configuration on block RAMB18E1_RAMB18E1"
(Xilinx Answer 39459) 12.4 EDK - My Base System Builder design fails timing on the SP605 board at 100 MHz
(Xilinx Answer 41545) 13.1 EDK, AXI_Ethernet_v2 - Transmit throttle error with TLAST asserting without TVALID and TREADY
(Xilinx Answer 40516) 12.4/13.1 EDK AXI_Ethernet - AXI Ethernet hardware needs extra delays for accessing the registers after a core reset
(Xilinx Answer 40651) 12.2 EDK, MPMC - Slight overshoot might occur on DQS/DQS_n in Virtex-6
(Xilinx Answer 40650) 12.2 EDK, MPMC, Virtex-6, DDR3 - On-Die Termination Setting C_MEM_ODT_TYPE does not seem to work correctly.
(Xilinx Answer 40653) 12.2 EDK, MPMC - Reduced drive output enable C_MEM_REDUCED_DRV not set correctly
(Xilinx Answer 39449) 12.3 EDK - Launching Questa from within XPS GUI
(Xilinx Answer 34381) 12.1 EDK - Why does the SDK provided lwIP echo server design not work?
(Xilinx Answer 40256) 13.1 EDK - Why is Create Import Peripheral (CIP) Wizard hanging?
(Xilinx Answer 40139) 12.1 EDK - make: *** [implementation/mb0_xps_reg_if_cntlr_wrapper.ngc] Segmentation fault
(Xilinx Answer 40430) 12.4 EDK - AXI IP reset signal is not identified correctly in the CIP Wizard
(Xilinx Answer 40703) 13.1 EDK - The Xilflash and Xilisf libraries do not compile
(Xilinx Answer 40682) 13.1 EDK - Why does SDK use 12 GB of swap memory?
(Xilinx Answer 41281) 13.1 EDK - Software register's read data keeps the same in axi4_lite IP generated by CIP Wizard
(Xilinx Answer 41363) 13.1 EDK - Incorrect Bus2IP_Resetn polarity in user_logic.v generated by CIP Wizard
(Xilinx Answer 37102) 12.4 Project Navigator - Design Summary is not updated after XMP/XPS/EDK changes
(Xilinx Answer 39489) 12.3 EDK - lwIP Echo Server example does not work with AXI Ethernet Lite systems
(Xilinx Answer 36359) 13.1 EDK - "ERROR:NgdBuild:76 - File "../implementation/pwm_lights_0_wrapper.ngc" cannot be..."


Known Issues in 13.1


(Xilinx Answer 40258) 13.x EDK - What patches are currently available for 13.x EDK?
(Xilinx Answer 39844) 13.1 EDK - How do I disconnect my AXI cache lines?
(Xilinx Answer 40206) 13.1 EDK, AXI_FIFO_MM_S - "ERROR:PhysDesignRules - Issue with pin connections and/or configuration on block RAMB18E1_RAMB18E1"
(Xilinx Answer 40207) 13.1 EDK, AXI Interconnect - "ERROR:EDK:3900 - Interconnect does not support downsizing directly from 1024-bit"
(Xilinx Answer 40256) 13.1 EDK - Why is Create Import Peripheral (CIP) Wizard hanging?
(Xilinx Answer 40257) 13.1 EDK - GUI Issues
(Xilinx Answer 40302) 13.1 EDK, AXI_USB2_Device - "ERROR:EDK - axi_usb2_device_0 - can't use empty string as operand of "/""
(Xilinx Answer 40424) 13.1 EDK, AXI_Ethernet - Constraint [system.ucf(85)]: NET "*/rx_client_clk" does not match any design objects
(Xilinx Answer 40682) 13.1 EDK - Why does SDK use 12 GB of swap memory?
(Xilinx Answer 40703) 13.1 EDK - Why do the Xilflash and Xilisf libraries not compile?
(Xilinx Answer 40863) 13.1 EDK - How do I use the new fault tolerant and ECC features in MicroBlaze and the LMB controllers?
(Xilinx Answer 39667) 12.1 EDK - "ERROR: Debug Operation Not Supported on the Target"
(Xilinx Answer 39489) 12.3 EDK - lwIP Echo Server example does not work with AXI Ethernet Lite systems
(Xilinx Answer 40139) 12.1 EDK - make: *** [implementation/mb0_xps_reg_if_cntlr_wrapper.ngc] Segmentation fault
(Xilinx Answer 40430) 12.4 EDK - AXI IP reset signal is not identified correctly in the CIP Wizard
(Xilinx Answer 40682) 13.1 EDK - Why does SDK use 12 GB of swap memory?
(Xilinx Answer 36359) 13.1 EDK - "ERROR:NgdBuild:76 - File "../implementation/pwm_lights_0_wrapper.ngc" cannot be..."
(Xilinx Answer 41281) 13.1 EDK - Software register's read data keeps the same in axi4_lite IP generated by CIP Wizard
(Xilinx Answer 41363) 13.1 EDK - Incorrect Bus2IP_Resetn polarity in user_logic.v generated by CIP Wizard
(Xilinx Answer 40650) 12.2 EDK, MPMC, Virtex-6, DDR3 - On-Die Termination Setting C_MEM_ODT_TYPE does not seem to work correctly
(Xilinx Answer 40651) 12.2 EDK, MPMC - Slight overshoot might occur on DQS/DQS_n in Virtex-6
(Xilinx Answer 40653) 12.2 EDK, MPMC - Reduced drive output enable C_MEM_REDUCED_DRV not set correctly
(Xilinx Answer 39459) 12.4 EDK - My Base System Builder design fails timing on the SP605 board at 100 MHz
(Xilinx Answer 40516) 12.4/13.1 EDK AXI_Ethernet - AXI Ethernet hardware needs extra delays for accessing the registers after a core reset
(Xilinx Answer 41545) 13.1 EDK, AXI_Ethernet_v2 - Transmit throttle error with TLAST asserting without TVALID and TREADY
(Xilinx Answer 40206) 13.1 EDK, AXI_FIFO_MM_S - "ERROR:PhysDesignRules - Issue with pin connections and/or configuration on block RAMB18E1_RAMB18E1"
(Xilinx Answer 39530) 12.3 EDK, xps_timer v1.02.a - Interrupt is not generated again after two timers output interrupt simultaneously
(Xilinx Answer 39300) 12.3 EDK, PLBv46_PCIe v4.05.a - Does not work in Root Complex mode
(Xilinx Answer 39456) Virtex-6 FPGA Integrated Block Wrapper for PCI Express - Delay Aligner Work-around
(Xilinx Answer 37634) 12.2 EDK, PPC440MC_DDR2 - WARNING:EDK - : Bit 8:9 of C_PPC440MC_CONTROL is set to 00

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AR# 39843
Date 10/02/2017
Status Active
Type General Article
Tools More Less