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AR# 39926

System Generator - ChipScope Pro - "ERROR:Xst:1617 - Processing TIMESPEC TS_ce_50000_e5b921f4_group_to_ce_50000_e5b921f4_group" with Chipscope Module

Description

Following error occurs if I generate HDL netlist from System Generator, and then synthesize auto-generated design in Project Navigator.

WARNING:Xst:1513 - No elements found for TNM 'ce_50000_e5b921f4_group' on object 'ce_50000_sg_x0'.
WARNING:Xst:2173 - Found black boxes on which forward tracing can not be performed on edge 'ce_50000_sg_x0':
led1_x0/counter/comp0.core_instance0
WARNING:Xst:2174 - These might be cores which have not been read
WARNING:Xst:2173 - Found black boxes on which forward tracing can not be performed on edge 'clk':
persistentdff_inst led1_x0/chipscope/i_ila led1_x0/counter1/comp1.core_instance1 led1_x0/counter/comp0.core_instance0
WARNING:Xst:2174 - These might be cores which have not been read
ERROR:Xst:1617 - Processing TIMESPEC TS_ce_50000_e5b921f4_group_to_ce_50000_e5b921f4_group: user TIMEGRP 'ce_50000_e5b921f4_group' must be previously defined in FROM/TO constraint.
ERROR:Xst:1489 - Constraint annotation failed.

Solution

This problem occurs when the ChipScope module is used in a System Generator design. It is generated as a black box by default in the design. TheCE driven to theChipScope cores can't be forward traced, so it errors out.

To fix this issue, check "read cores" in XST properties. This will read the ChipScope netlist in XST and allow the net to be traced.

AR# 39926
Date Created 04/08/2011
Last Updated 12/15/2012
Status Active
Type General Article
Tools
  • System Generator for DSP - 12.3
IP
  • ChipScope ICON
  • ChipScope ILA