Using the Synopsys VCS simulator to perform back-annotated timing simulations of certain configurations of the Virtex-6 FPGA Embedded Tri-Mode Ethernet MAC can result in the following error:
Specifically, the TEMAC_SINGLE SecureIP model's EMACPHYTXGMIIMIICLKOUT clock output fails to toggle in some cases, resulting in a lack of transmitter operation.
This is due to pulse-swallowing of the PHYEMACGTXCLK input within the X_TEMAC_SINGLE simprim instance, and is limited to timing simulations when using the Synopsys VCS simulator.
This issue has been seen with the Virtex-6 FPGA Embedded Tri-Mode Ethernet MAC v1.5 and v2.1 wrappers in ISE 12.x and ISE 13.x.
To work around this problem, use another supported simulator to perform back-annotated timing simulations.
Alternatively, if use of the Synopsys VCS simulator is desired, you can do one of the following: