UPGRADE YOUR BROWSER

We have detected your current browser version is not the latest one. Xilinx.com uses the latest web technologies to bring you the best online experience possible. Please upgrade to a Xilinx.com supported browser:Chrome, Firefox, Internet Explorer 11, Safari. Thank you!

AR# 39978

Design Assistant for XST - Help instantiating custom modules

Description

Please refer to this answer record for help instantiating custom modules.

Note: This Answer Record is a part of the Xilinx Solution Center for XST (Xilinx Answer 38927). The Xilinx Solution Center for XST is available to address all questions related to XST. Whether you are starting a new design or troubleshooting a problem, use the Solution Center for XST to guide you to the right information.

Solution

Below is a checklist to verify when instantiating a custom module in VHDL or Verilog:

VHDL:
  • Ensure that the port names are consistent between the component declaration, instantiation and entity declaration.
  • Ensure that the port widths are consistent between the component declaration, instantiation and entity declaration.
  • Ensure that the port directions are consistent between the component declaration, instantiation and entity declaration.
  • Ensure that semicolons are placed after every port except for the last port in the component declaration and the entity declaration.
  • Ensure that commas are placed after every connection in an instantiation except for the last connection.
  • Capitalization only matters if you are instantiating a Verilog module in VHDL.
  • In the instantiation, remember that the instance name is before the colon. The component name comes after the colon.
  • Component declarations are either placed in a package, or in the same file as the instantiation between the architecture and begin statement.
  • If the lower level module is compiled to another library, remember to include this library.
Verilog:
  • Capitalization must be consistent.
  • Ensure that the port names are consistent between the component declaration, instantiation and entity declaration.
  • Ensure that the port widths are consistent between the component declaration, instantiation and entity declaration.
  • Ensure that the port directions are consistent between the component declaration, instantiation and entity declaration.
  • Ensure that commas are placed after every connection except for the last connection

Linked Answer Records

Master Answer Records

Answer Number Answer Title Version Found Version Resolved
38927 Xilinx Solution Center for XST N/A N/A

Associated Answer Records

Answer Number Answer Title Version Found Version Resolved
39648 Design Assistant for XST - Instantiating modules, primitives, black boxes and Xilinx Cores. N/A N/A
AR# 39978
Date Created 01/08/2011
Last Updated 12/15/2012
Status Active
Type General Article