The following items represent a collection of issues that have been identified in the 13.4 ISE design tools and are related to Spartan-6 FPGA. There might be issues which are present and are not listed here. If you discover an issue that is not on this list, please open a WebCase with Xilinx Technical Support.
It is strongly recommended that designs be re-synthesized (and IP cores re-implemented) when re-implementing for production using the software that has production status speed files for the target device. This ensures that the changes to DRCs, timing models, clock topologies, and other fixes in software are picked up.
(Xilinx Answer 45400) Spartan-6 - AXI_HWICAP locks up if I attempt to access it immediately after configuration
(Xilinx Answer 40387) Spartan-6 Configuration - GCLK0 input can glitch at the end of configuration
(Xilinx Answer 41877) Spartan-6 - iMPACT indirect SPI Flash Programming Failed in multiple Spartan-6 FPGA devices in SPI Daisy Chain configuration mode.
(Xilinx Answer 44174) - Design Advisory for techniques on properly synchronizing flip-flops and SRLs after startup
(Xilinx Answer 35237) Spartan-6 FPGA GTP Transceiver - SelectIO to GTP Crosstalk/SSO Guidelines
(Xilinx Answer 38408) Spartan-6 Design Advisory - IODELAY2 - early edge delays, late edge delays, and single data bit corruption
(Xilinx Answer 44192) - Design Advisory for Spartan-6 FPGA Speed File - Updates for Block RAM fMAX in Lower Power -1L Devices
(Xilinx Answer 44193) - Design Advisory for Spartan-6 FPGA Speed File - Updates for DCM Phase Alignment
(Xilinx Answer 34856) - Design Advisory for the Spartan-6 FPGA Master Answer Record
Spartan-6 Production Errata and Product Change Notification (PCN)
Improving Performance in Spartan-6 FPGA Designs White Paper (WP311)
Targeting and Re-targeting Guide for Spartan-6 FPGAs White Paper (WP309)
01/18/2012 - Updates for 13.4 release
10/26/2011 - Updates for 13.3 release
07/06/2011 - Updates for 13.2 release
03/01/2011 - Initial release for 13.1