AR# 40009

FIFO Generator v6.2 - The PROG_FULL flag asserts 2 clock cycles early

Description


The PROG_FULL flag is asserted two clock cycles early with respect to the wr_data_count signal.

For example, I have a test case where for a 4096 deep FIFO,  the Full Threshold Assert Value is set to 2048.

I have confirmed in Behavioral and Timing Simulations that the PROG_FULL flag will assert when the wr_data_count signal reaches a value of 2046.

The datasheet does not explain explicitly when the PROG_FULL should be asserted with respect to the wr_data_count signal.

However, the wr_data_count signal is what I would use to determine the state of the FIFO.

This behavior should either be changed or documented to let customers know what to expect.

A work around is to simple add two registers after the PROG_FULL output.

Solution

This is expected behavior.

For the user configuration, "use extra logic" should be set to true to get more accurate information for wr_data_count.

This is explained in the Data Counts section of the user guide
AR# 40009
Date 09/10/2014
Status Active
Type General Article
IP