AR# 40020: ISE Design Suite 12 DSP Tools (System Generator for DSP) (12.4) - README
AR# 40020
ISE Design Suite 12 DSP Tools (System Generator for DSP) (12.4) - README
Description
This Answer Record contains the Release Notes and Known Issues for System Generator for DSP 12.4.
Solution
For System Generator for DSP Release Notes from other versions, see (Xilinx Answer 29595).
This README Answer Record contains installation instructions and a list of the issues fixed in the System Generator for DSP 12.4. A successful installation of ISE Design Suite 12.4 changes your design tools version number to 12.4 (verify by running xlVersion at the MATLAB prompt).
Release Notes and Known Issues in System Generator for DSP 12.4
Please read the documentation because it answers questions that you might have about changes to the functionality or the look from previous versions of System Generator for DSP. The System Generator User Guide is accessible in PDF format at: http://www.xilinx.com/ise/optional_prod/system_generator.htm
Starting with the 11.2 release, further development of the AccelDSP synthesis tool has been discontinued. You can continue to use this version of the tool with ISE Design Suite 11. The AccelDSP synthesis tool is not included in ISE Design Suite 12.
Frequently Asked Questions
Installation and setup (Xilinx Answer 17966) - What software is required to install System Generator for DSP? (Xilinx Answer 32257) - How can I tell if the DSP Tools are installed and configured for use in MATLAB? (Xilinx Answer 24842) - How can I switch between multiple versions of System Generator for one MATLAB installation? (Xilinx Answer 32258) - How can I install just the DSP Tools without reinstalling all of the ISE Design Tools? (Xilinx Answer 25306) - Which version of System Generator supports the latest version of MATLAB? (Xilinx Answer 31095) - Why do I receive "Error while executing C MEX S-function 'sysgen', (mdlTerminate). Unexpected unknown exception from MEX file" when I simulate my System Generator model? How do I set up my system environment properly? (Xilinx Answer 33788) - How does System Generator license checkout work?
MATLAB and Simulink interaction (Xilinx Answer 31933) - Why do I receive an error message stating "continuous sample times are not allowed" when driving a Simulink Spectrum Scope with Xilinx System Generator blocks? (Xilinx Answer 30131) - Why is the sample rate passed to Simulink blocks from my gateway out different than the sample rate passed to my System Generator blocks? (Xilinx Answer 21750) - Why do I receive a "xlSimulationRequired" or "Reference to a cleared variable sysgen_return_status" error when I try to generate the design? (Xilinx Answer 23000) - An indeterminate input data (also known as a NAN) error occurs when design is simulated. (Xilinx Answer 24616) - Why am I unable to access the quantization parameters in the FDATool in System Generator? (Xilinx Answer 25255) - Why do I receive a Simulink message stating, "Use of this data type requires a fixed-point license, but license checkout failed"? (Xilinx Answer 23328) - What is the recommended Simulink simulation solver? Why do I see incorrect behavior when a fixed-step solver is used? (Xilinx Answer 32810) - Why does my data not appear downsampled when I use "first value of frame" with a latency of 0 with the downsample block? (Xilinx Answer 32856) - Why do I receive an internal error or see MATLAB crash if I use the Simulink Simulation option "Accelerator"?
Third-party Synthesis Tools (Xilinx Answer 24273) - I cannot generate an NGC, Bitstream, Timing Analysis, or Hardware in the Loop target when using Synplify as my synthesis tool. Why? (Xilinx Answer 31112) - Why do I receive the message "Failed to execute command "project set {Synthesis Tool} {Synplify Pro (VHDL/Verilog)}"" when trying to use Synplify Pro for my synthesis tool from System Generator? (Xilinx Answer 29170) - Why are there simulation mismatches at the beginning of the HDL simulation generated from System Generator for DSP when Synplify is used for synthesis?
General (Xilinx Answer 24257) - Why do I see an instantiated register called "xlpersistentdff" in a System Generator for DSP design? (Xilinx Answer 19599) - JTAG Hardware Co-Sim with non-Xilinx parts in the chain causes error. (Xilinx Answer 29430) - Why do I receive a standard exception error message when I generate my model? (Xilinx Answer 35474) - How can I simulate my Multiple clock domain System Generator design in VHDL?
Known Issues (Xilinx Answer 39632) - How do I enter multiple instructions in the DSP48 Macro v2.0 GUI with Windows 7 64-bit? (Xilinx Answer 39739) - FIR Compiler v6.1 - When ratetype = fixed_fractional, Hardware Oversampling format always set to "Sample Period" mode (Xilinx Answer 39746) - Cannot dismiss dialogs, models or subsystems while Help is open, if help was spawned in its own Firefox browser (Xilinx Answer 36522) - Why do I get errors during generation if my user name contains non-English characters? (Xilinx Answer 36112) - I am unable to meet timing with the clock enable (CE) nets in my System Generator design. (Xilinx Answer 34135) - Why do I get a java exception error when I select "New Compilation Target" in the token? (Xilinx Answer 34287) - The memory usage increases each time a model is simulated and eventually will crash MATLAB. (Xilinx Answer 35268) - "ERROR:Portability:3 - This Xilinx application has run out of memory or has encountered a memory conflict." (Xilinx Answer 36039) - Why do I see simulation mismatches coming out of the Interleaver/Deinterleaver v6.0 block?
Linux Only
(Xilinx Answer 32173) - Why is the System Generator blockset empty when I attempt to open it in Simulink when running on Linux?