The UCF provided with the LogiCORE IP Tri-Mode Ethernet MACand Virtex-6 FPGA Embedded Tri-mode Ethernet MAC Wrapper includes an example OFFSET constraint which enforces clock-data alignment on the receive side physical interface to within a specific data valid window.
While helpful in determining alignment, that data valid window may not meet the setup and hold requirements of the GMII or RGMII specifications. A more relaxed window is provided for some devices, primarily because of clock uncertainty resulting from the receive clock's IODELAY instance.
This answer record applies to all versions of the LogiCORE IP Tri-Mode Ethernet MAC and v2.1 and later of the Virtex-6 FPGA Embedded Tri-mode Ethernet MAC Wrapper. For earlier versions of the Virtex-6 FPGA Embedded Tri-mode Ethernet MAC Wrapper please see (Xilinx Answer 33195).
Proper tuning of the IDELAY taps is recommended for all designs.For details on finding the ideal settings for your design, see the LogiCORE IP Tri-Mode Ethernet MAC v5.1 User Guide (UG777) or theVirtex-6 FPGA Embedded TEMAC Solution User Guide (UG800).
Adjust the OFFSET constraint to conform to the appropriate specification. For GMII modes, ensure that the constraint uses: "IN 2 ns VALID 2 ns". For RGMII modes, ensure that the constraint uses: "IN 1 ns VALID 2 ns".
For Virtex-6 lower power devices (-1L speed grade) and some Virtex-6 HXT devices, implementation of the GMII physical interface will not meet the receiver timing specification, and implementation of the RGMII physical interface receiver timing is marginal. However, proper IODELAY tuning and sufficient system margin can allow for a working system. Be sure to analyze your PHY's timing characteristics and system margin during IODELAY tuning.