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AR# 40037

Virtex-5/Virtex-6 - RAMB18 and RAMB38 data width in SDP and TDP modes


In Virtex-5/Virtex-6 FPGA, a block RAM stores up to 36k bits of data (RAMB36) and it can be configured as two independent 18k RAMs (RAMB18). 

Each block RAM can be configured as true dual-port (TDP), simple dual-port (SDP) and single port.


Each RAMB18/RAMB36 can have independent read width and write width in TDP mode.

When a Virtex-5 Block RAM is used in SDP mode the READ and WRITE widths must be equal.

Therefore, when a RAMB18 is configured with independent read and write widths with Block Memory Generator (IP core), it cannot choose an SDP and will choose a TDP RAMB36, which causes the BRAM resource to be doubled.

Virtex-6 block RAM in SDP mode can have one port of optional width. The other port is a fixed width of 36 bits for RAMB18 and 72 bits for RAMB36.

AR# 40037
Date 08/16/2017
Status Active
Type General Article
  • Virtex-6 CXT
  • Virtex-6 HXT
  • Virtex-6 LX
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  • Virtex-6 LXT
  • Virtex-6 SXT
  • Virtex-6Q
  • Virtex-5 FXT
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  • Virtex-5 SXT
  • Virtex-5 TXT
  • Virtex-5Q
  • Virtex-5QV
  • Less
  • Block Memory Generator
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